Using edge-valued decision diagrams for symbolic generation of shortest paths

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2517, Issue , 2002, Pages 256-273

  Ciardo, Gianfranco ^a   Siminiceanu, Radu ^a  

^a The College of William and Mary   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL EFFICIENCY; COMPUTER AIDED DESIGN; FORMAL METHODS; GRAPHIC METHODS;

DECISION DIAGRAM; DISTANCE FUNCTIONS; INITIAL STATE; REACHABILITY GRAPHS; SHORTEST PATH; SYMBOLIC CONSTRUCTION;

GRAPH THEORY;

EID: 84948133311     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-36126-x_16     Document Type: Conference Paper

References (24)

1. P. A. Abdulla, P. Bjesse, and N. Een. Symbolic reachability analysis based on SAT-solvers. In S. Graf and M. Schwartzbach, editors, Proc. Tools and Algorithms for the Construction and Analysis of Systems TACAS, Berlin, Germany, volume 1785 of LNCS, pages 411–425. Springer-Verlag, 2000.
2. V. Amoia, G. De Micheli, and M. Santomauro. Computer-oriented formulation of transition-rate matrices via Kronecker algebra. IEEE Trans. Rel., 30:123–132, June 1981.
3. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Maciii, A. Pardo, and F. Somenzi. Algebraic decision diagrams and their applications. Formal Methods in System Design, 10(2/3):171–206, Apr. 1997.
4. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. LNCS, 1579:193–207, 1999.
5. R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comp., 35(8):677–691, Aug. 1986.
6. R. E. Bryant and Y.-A. Chen. Verification of arithmetic circuits with binary moment diagrams. In Proc. Of Design Automation Conf. (DAC), pages 535–541, 1995.
7. J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and L. J. Hwang. Symbolic model checking: 1020 states and beyond. In Proc. 5th Annual IEEE Symp. On Logic in Computer Science, pages 428–439, Philadelphia, PA, 4–7 June 1990. IEEE Comp. Soc. Press.
8. G. Ciardo, R. L. Jones, A. S. Miner, and R. Siminiceanu. SMART: Stochastic Model Analyzer for Reliability and Timing. In P. Kemper, editor, Tools of Aachen 2001 Int. Multiconference on Measurement, Modelling and Evaluation of Computer-Communication Systems, pages 29–34, Aachen, Germany, Sept. 2001.
9. G. Ciardo, G. Luettgen, and R. Siminiceanu. Efficient symbolic state-space construction for asynchronous systems. In M. Nielsen and D. Simpson, editors, Application and Theory of Petri Nets 2000 (Proc. 21th Int. Conf. On Applications and Theory of Petri Nets, Aarhus, Denmark), LNCS 1825, pages 103–122. Springer-Verlag, June 2000.
10. G. Ciardo, G. Luettgen, and R. Siminiceanu. Saturation: An efficient iteration strategy for symbolic state space generation. In T. Margaria and W. Yi, editors, Proc. Tools and Algorithms for the Construction and Analysis of Systems (TACAS), LNCS 2031, pages 328–342, Genova, Italy, Apr. 2001. Springer-Verlag.
11. E. Clarke, E. Emerson, and A. Sistla. Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Trans. Progr. Lang. And Syst., 8(2):244–263, Apr. 1986.
12. E. Clarke and X. Zhao. Word level symbolic model checking: A new approach for verifying arithmetic circuits. Technical Report CS-95-161, Carnegie Mellon University, School of Computer Science, May 1995.
13. E. M. Clarke, O. Grumberg, and D. A. Peled. Model Checking. MIT Press, 1999.
14. R. Drechsler and B. Becker. Overview of decision diagrams. IEE Proc.-Comput. Digit. Tech., 144(3):187–193, May 1997.
15. E.M. Clarke, O. Grumberg, K.L. McMillan, and X. Zhao. Efficient generation of counterexamples and witnesses in symbolic model checking. In 32nd Design Automation Conference (DAC 95), pages 427–432, San Francisco, CA, USA, 1995.
16. A. Geser, J. Knoop, G. Lüttgen, B. Steffen, and O. Rüthing. Chaotic fixed point iterations. Technical Report MIP-9403, Univ. Of Passau, 1994.
17. R. Hojati, R. K. Brayton, and R. P. Kurshan. BDD-based debugging of designs using language containment and fair CTL. In C. Courcoubetis, editor, Computer Aided Verification (CAV’93), volume 697 Of LNCS, pages 41–58, Elounda, Greece, June/July 1993. Springer-Verlag.
18. J.R. Burch, E.M. Clarke, and D.E. Long. Symbolic model checking with partitioned transition relations. In A. Halaas and P.B. Denyer, editors, Int. Conference on Very Large Scale Integration, pages 49–58, Edinburgh, Scotland, Aug. 1991. IFIP Transactions, North-Holland.
19. T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli. Multi-valued decision diagrams: theory and applications. Multiple-Valued Logic, 4(1–2):9–62, 1998.
20. Y.-T. Lai, M. Pedram, and B. K. Vrudhula. Formal verification using edge-valued binary decision diagrams. IEEE Trans. Comp., 45:247–255, 1996.
21. Y.-T. Lai and S. Sastry. Edge-valued binary decision diagrams for multi-level hierarchical verification. In Proceedings of the 29th Conference on Design Automation, pages 608–613, Los Alamitos, CA, USA, June 1992. IEEE Computer Society Press.
22. A. S. Miner and G. Ciardo. Efficient reachability set generation and storage using decision diagrams. In H. Kleijn and S. Donatelli, editors, Application and Theory of Petri Nets 1999 (Proc. 20th Int. Conf. On Applications and Theory of Petri Nets, Williamsburg, VA, USA), LNCS 1639, pages 6–25. Springer-Verlag, June 1999.
23. T. Murata. Petri Nets: properties, analysis and applications. Proc. Of the IEEE, 77(4):541–579, Apr. 1989.
24. P. F. Williams, A. Biere, E. M. Clarke, and A. Gupta. Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. In Proceedings of CAV’00, pages 124–138, 2000.