Formal verification using edge-valued binary decision diagrams

IEEE Transactions on Computers

Volumn 45, Issue 2, 1996, Pages 247-255

  Lai, Yung Te ^a   Pedram, Massoud ^b   Vrudhula, Sarma B K ^c  

^a Hitachi Micro Systems Inc   (United States)

^b University of Southern California   (United States)

^c University of Arizona   (United States)

Author keywords

Binary decision diagrams; Boolean functions; Pseudo Boolean functions; Verification

Indexed keywords

EID: 2342578484     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.485378     Document Type: Article

References (22)

1. G.V. Bochmann, "Hardware specification with temporal logic: An example," IEEE Trans. Computers, vol. 31, no. 3, pp. 223-231, Mar. 1982.
2. R.T. Boute, "Representational and denotational semantics of digital systems," IEEE Trans. Computers, vol. 38, no. 7, pp. 986-999, July 1989.
3. K.S. Brace, R.L. Rudell, and R.E. Bryant, "Efficient implementation of a BDD package," Proc. 27th Design Automation Conf., pp. 40-45, 1990.
4. R.E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986.
5. R.E. Bryant, D. Beatty, K. Brace, K. Cho, and T. Sheffler, "COSMOS: A compiled simulator for MOS circuits," Proc. 24th Design Automation Conf., pp. 9-16, 1987.
6. R.E. Bryant, "Symbolic Boolean manipulation with ordered binary-decision diagrams," Computing Surveys, vol. 24, no. 3, pp. 293-318, Sept. 1992.
7. E.M. Clarke, E.A. Emerson, and A.P. Sistla, "Automatic verification of finite-state concurrent systems using temporal logic specifications," ACM Trans. Prog. Lang. Syst., vol. 8, no. 2, 1986.
8. E.M. Clarke, M. Fujita, P.C. McGeer, K.L. McMillan, and J.C.-Y. Yang, "Multi-terminal binary decision diagrams: An efficient data structure for matrix representation," Int'l Workshop Logic Synthesis, pp. 6a:1-15, May 1993.
9. E.M. Clarke, K.L. McMillan, X. Zhao, M. Fujita, and J.C.-Y. Yang, "Spectral transforms for large Boolean functions with applications to technology mapping," Proc. 30th Design Automation Conf., pp. 54-60, 1993.
10. O. Coudert, C. Berthet, and J.C. Madre, "Verification of synchronous sequential machines based on symbolic execution," Proc. Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France, June 1989.
11. M.J.C. Gordon, "Why higher-order logic is a good formalism for specifying and verifying hardware," Formal Aspects of VLSI Designs, G.J. Milne and P.A. Subrahmanyam, eds., pp. 153-177, 1986.
12. P.L. Hammer and S. Rudeanu, Boolean Methods in Operations Research and Related Areas. Heidelberg: Springer-Verlag, 1968.
13. Y-T. Lai and S. Sastry (S.B.K. Vrudhula), "Edge-valued binary decision diagrams for multi-level hierarchical verification," Proc. 29th Design Automation Conf., pp. 608-613, 1992.
14. Y-T. Lai, S. Sastry (S.B.K. Vrudhula), and M. Pedram, "Boolean matching using binary decision diagrams with applications to logic synthesis and verification," Proc. Int'l Conf. Computer Design, pp. 452-458, 1992.
15. Y-T. Lai, M. Pedram, and S. Sastry (S.B.K. Vrudhula), "BDD based decomposition of logic functions with application to FPGA synthesis," Proc. 30th Design Automation Conf, pp. 642-647, 1993.
16. Y-T. Lai, M. Pedram, and S. Sastry (S.B.K. Vrudhula), "FGILP: An integer linear program solver based on function graphs," Proc. Int'l Conf. Computer Aided Design, 1993.
17. Y-T. Lai, "Logic verification and synthesis using function graphs," PhD dissertation, Computer Eng., Univ. of Southern California, Dec. 1993.
18. Y-T. Lai, M. Pedram, and S.B.K. Vrudhula, "EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition," IEEE Trans. Computer Aided Design, vol. 13, no. 8, pp. 959-975, Aug. 1994.
19. H-T. Liaw and C-S Lin, "On the OBDD-representation of general Boolean functions," IEEE Trans. Computers, vol. 41, no. 6, pp. 661-664, June 1992.
20. G.J. Milne, ,"CIRCAL and the representation of communication, concurrency, and time," ACM Trans. Programming Languages and Systems, vol. 7, no. 2, pp. 270-298, Apr. 1985.
21. A. Srinivasan, T. Kam, S. Malik, and R. Brayton, "Algorithms for discrete function manipulation," Proc. Int'l Conf. Computer Aided Design, pp. 92-95, 1990.
22. Texas Instruments, "The TTL data book for design engineers," Texas Instruments, 1984.