-
1
-
-
0022151809
-
An optimal instruction-scheduling model for a class of vector processors
-
S. Arya. An optimal instruction-scheduling model for a class of vector processors. IEEE Transactions on Computers, C-34(11):981–995, 1985.
-
(1985)
IEEE Transactions on Computers
, Issue.11
, pp. 981-995
-
-
Arya, S.1
-
2
-
-
0024304123
-
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
-
D. Bernstein and I. Gertner. Scheduling expressions on a pipelined processor with a maximal delay of one cycle. ACM Transactions on Programming Languages and Systems, 11(1):57–66, 1989.
-
(1989)
ACM Transactions on Programming Languages and Systems
, vol.11
, Issue.1
, pp. 57-66
-
-
Bernstein, D.1
Gertner, I.2
-
3
-
-
0024735520
-
On the complexity of scheduling problems for parallel/pipelined machines
-
D. Bernstein, M. Rodeh, and I. Gertner. On the complexity of scheduling problems for parallel/pipelined machines. IEEE Transactions on Computers, 38(9):1308–1313, 1989.
-
(1989)
IEEE Transactions on Computers
, vol.38
, Issue.9
, pp. 1308-1313
-
-
Bernstein, D.1
Rodeh, M.2
Gertner, I.3
-
5
-
-
0031268141
-
Using integer programming for instruction scheduling and register allocation in multi-issue processors
-
C.-M. Chang, C.-M. Chen, and C.-T. King. Using integer programming for instruction scheduling and register allocation in multi-issue processors. Computers and Mathematics with Applications, 34(9):1–14, 1997.
-
(1997)
Computers and Mathematics with Applications
, vol.34
, Issue.9
, pp. 1-14
-
-
Chang, C.-M.1
Chen, C.-M.2
King, C.-T.3
-
6
-
-
0025228149
-
Enhancement schemes for constraint processing: Backjumping, learning, and cutset decomposition
-
R. Dechter. Enhancement schemes for constraint processing: Backjumping, learning, and cutset decomposition. Artificial Intelligence, 41:273–312, 1990.
-
(1990)
Artificial Intelligence
, vol.41
, pp. 273-312
-
-
Dechter, R.1
-
10
-
-
0032044670
-
Scheduling expression DAGs for minimal register need
-
C. W. Kessler. Scheduling expression DAGs for minimal register need. Computer Languages, 24(1):33–53, 1998.
-
(1998)
Computer Languages
, vol.24
, Issue.1
, pp. 33-53
-
-
Kessler, C.W.1
-
11
-
-
84947903716
-
Constraint-based scheduling: A theoretical comparison of resource constraint propagation rules
-
Brighton, UK, August
-
C. Le Pape and P. Baptiste. Constraint-based scheduling: A theoretical comparison of resource constraint propagation rules. In Proceedings of the ECAI Workshop on Non-Binary Constraints, Brighton, UK, August 1998.
-
Proceedings of the ECAI Workshop on Non-Binary Constraints
, pp. 1998
-
-
Le Pape, C.1
Baptiste, P.2
-
14
-
-
0031102303
-
Time-constrained code compaction for DSPs
-
R. Leupers and P. Marwedel. Time-constrained code compaction for DSPs. IEEE Trans. VLSI Systems, 5(1):112–122, 1997.
-
(1997)
IEEE Trans. VLSI Systems
, vol.5
, Issue.1
, pp. 112-122
-
-
Leupers, R.1
Marwedel, P.2
-
19
-
-
84930633981
-
Singleton consistencies
-
Singapore, September
-
P. Prosser, K. Stergiou, and T. Walsh. Singleton consistencies. In Proceedings of the Sixth International Conference on Principles and Practice of Constraint Programming, pages 353–368, Singapore, September 2000.
-
(2000)
Proceedings of the Sixth International Conference on Principles and Practice of Constraint Programming
, pp. 353-368
-
-
Prosser, P.1
Stergiou, K.2
Walsh, T.3
-
21
-
-
17144420879
-
Optimal instruction scheduling using integer programming
-
Vancouver, BC
-
K. Wilken, J. Liu, and M. Heffernan. Optimal instruction scheduling using integer programming. In Proceedings of the SIGPLAN 2000 Conference on Programming Language Design and Implementation (PLDI), pages 121–133, Vancouver, BC, June 2000.
-
(2000)
Proceedings of the SIGPLAN 2000 Conference on Programming Language Design and Implementation (PLDI)
, pp. 121-133
-
-
Wilken, K.1
Liu, J.2
Heffernan, M.3
-
22
-
-
84945954903
-
Instruction scheduling with timing constraints on a single RISC processor with 0/1latencies
-
Singapore, September
-
H. Wu, J. Jaffar, and R. Yap. Instruction scheduling with timing constraints on a single RISC processor with 0/1latencies. In Proceedings of the Sixth International Conference on Principles and Practice of Constraint Programming, pages 457–469, Singapore, September 2000.
-
(2000)
Proceedings of the Sixth International Conference on Principles and Practice of Constraint Programming
, pp. 457-469
-
-
Wu, H.1
Jaffar, J.2
Yap, R.3
|