A system level implementation of Rijndael on a memory-slot based FPGA card

Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002

Volumn , Issue , 2002, Pages 102-109

  Tong, D K Y ^a   Lo, Pui Sze ^a   Lee, Kin Hong ^a   Leong, P H W ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PRIVACY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

ADVANCED ENCRYPTION STANDARD; HIGH PERFORMANCE IMPLEMENTATIONS; MEMORY OPERATIONS; NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY; RECONFIGURABLE COMPUTING; RIJNDAEL ALGORITHM; STREAMING SIMD EXTENSIONS; SYSTEM-LEVEL PERFORMANCE;

CRYPTOGRAPHY;

EID: 84946074366     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2002.1188670     Document Type: Conference Paper

References (10)

1. nd ed., 1996.
2. B. Gladman: The AES Algorithm (Rijndael) in C and C++: URL: http://fp.gladman.plus.com/crytography-technology/rijndael/index.htm, 2001.
3. M. McLoone, J.V McCanny: High Performance Single-Chip FPGA Rijndael Algorithm Implementations, CHES 2001, pp. 65-76.
4. A.J. Elbert, E. Yip, B. Chetwynd, C. Paar. An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, IEEE Transactions on VLSI, August 2001, vol. 9, no. 4, pp. 545-557.
5. V. Fischer, M. Drutarovsky: Two Methods of Rijndael implementation in Reconfigurable Hardware, CHES 2001, pp. 77-92.
6. J. Daemen, V. Rijnmen: The Rijndael Block Cipher AES Proposal, Document version 2, September 03, 1999 (available from http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf).
7. P. H. W. Leong, M. P. Leong, O. Y. H. Cheung, T. Tung, C. M. Kwok, M. Y. Wong, K. H. Lee: Pilchard - A Reconfigurable Computer Platform with Memory Slot Interface, FCCM 2001 (to appear).
8. K. Gaj. P. Chodowiec: Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware: The Third Advanced Encryption Standard Candidate Conference, April 13-14, 2000, New York, USA.
9. A. Dandalis, V. K. Prasanna, J. D. P. Rolim: A Comparative Study of Performance of AES Candidates Using FPGAs: The Third Advanced Encryption Standard Candidate Conference, April 13-14, 2000, New York, USA.
10. SGI, "Optimizing CPU to Memory Accesseson the SGI Visual Workstations 320 and 540", http://www.sgi.com/developers/technology/irix/resources/asc-cpu.html