Aggressive compiler optimization and parallelization with thread-level speculation

Proceedings of the International Conference on Parallel Processing

Volumn 2003-January, Issue , 2003, Pages 607-614

  Chen, Li Ling ^a   Wu, Youfeng ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Collaboration; Dynamic compiler; Dynamic scheduling; Flow graphs; Hardware; Optimizing compilers; Performance gain; Program processors; Runtime; Yarn

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; EMBEDDED SYSTEMS; FLOW GRAPHS; GRAPHIC METHODS; HARDWARE; PROGRAM PROCESSORS; YARN;

COLLABORATION; DYNAMIC COMPILER; DYNAMIC SCHEDULING; OPTIMIZING COMPILERS; PERFORMANCE GAIN; RUNTIMES;

PROGRAM COMPILERS;

EID: 84944748106     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2003.1240629     Document Type: Conference Paper

References (18)

1. Sanjay J. Patel and Steven S. Lumetta, "rePlay: A Hardware Framework for Dynamic Program Optimization," CRHC Technical Report Draft, December 1999.
2. Gupta, R.; Benson, D.A.; Fang, J.Z., "Path profile guided partial dead code elimination using predication," International Conference on Parallel Architectures and Compilation Techniques., 1997. Proceedings., 1997 International Conference on, 1997, Page(s): 102-113
3. V. Krishnan, J. Torrellas, "A chip-multiprocessor architecture with speculative multithreading," IEEE Transactions on Computers, Volume: 48 Issue: 9, pp. 866-880, Sept. 1999
4. H. Akkary, H, M.A. Driscoll, "A dynamic multithreading processor," In Proceedings of 31st Annual ACM/IEEE International Symposium on Microarchitecture, pp. 226-236, 1998
5. Wen-mei W. Hwu, et al, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation." The Journal of Supercomputing, Kluwer Academic Publishers, 1993, pp. 229-248
6. Intel Corp, "IA-64 Application Developers Architecture Guide," May 1999.
7. Sanjay J. Patel, et al, " Increasing the Size of Atomic Instruction Blocks Using Control Flow Assertions." MICRO-33, Dec 2000, pp.303-313.
8. J. A. Fisher, "Trace scheduling: A technique for global microcode compaction," IEEE Transactions on Computers, C-30(7):478-490, July 1981.
9. Satish B. Rao, "Faster algorithms for finding small edge cuts in planar graphs," Proceedings of the twenty-fourth annual ACM symposium on Theory of computing, 1992, Pages 229-240
10. S. Gopal, T. Vijayakumar, J. Smith, G. Sohi, "Speculative Versioning Cache",. In Proceedings of HPCA-IV, pp. 195-207, January 1998,store buffer
11. Thomas Ball and James R. Larus, "Optimally profiling and tracing problems," ACM Trans. Program. Lang. System. 16, 4 (Jul. 1994), Pages 1319-1360.
12. st Annual ACM/IEEE International Symposium on Microarchitecture, 1998, Pages 81-92.
13. th Annual International Symposium on Microarchitecture, 1995, Pages 158-168.
14. th International Symposium on Microarchitecutre, 2002, Pages 85-96.
15. rd Internation Symposium on Microarchitecture, 2000, Pages 303-315.
16. th ISCA, Vancouver, BC, Canada.
17. Jeffey T. Oplinger, D. Heine, and Monica Lam, "In search of speculative thread-level parallelism," International Conference on Parallel Architectures and Compilation Techniques, 1999, Pages: 303-313 IEEE.
18. Li-Ling Chen and Youfeng Wu, "Fast Forward: Aggressive Compiler Optimization with Speculative Multi-Threaded Support", Workshop on Multithreaded Execution, Architecture and Compilation, in conjunction with Micro- 33, Dec. 2000.