High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 89-95

  Bhattacharya, S ^a   Chatterjee, A ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Assembly; Costs; Testing; Very large scale integration

Indexed keywords

ANALOG INTEGRATED CIRCUITS; ASSEMBLY; COSTS; INTEGRATED CIRCUIT DESIGN; INTEGRATION TESTING; TESTING; VLSI CIRCUITS;

CO-OPTIMIZATION; LOW SPEED; PACKAGE TEST; TEST COST; TESTING PROCESS; TRANSIENT SIGNAL; WAFER PROBES; WAVE FORMS;

PROBES;

EID: 84943554243     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197638     Document Type: Conference Paper

References (10)

1. J.B.Brockman and S.W.Director, "Predictive Subset Testing: optimizing IC parametric performance for quality, cost and yield," IEEE Tran. on Semiconductor Manufacturing, pp. 104-113, 2,1989.
2. L.Milor and V.Viswananathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Tran. on Computer Aided Design, pp.114-130, Vol. 8, 1989.
3. N.Nagi, A.Chatterjee, A.Balivada and J.A.Abraham, "Fault based automatic test generator for linear analog devices," Intl. Conf. on Computer-Aided Design, pp.88-91, 1993.
4. M.Salamani, B.Kaminska and G.Quesnel, " An integrated approach for analog circuit testing with minimum number of detected parameters," Intl. Test Conf., pp. 631-640, 1994.
5. Sheng-Jen Tsai, "Test vector generation for linear analog devices," Proc., IEEE Intl. test conf., pp.592-597, 1991.
6. A.Balivada, J.Chen and J.A.Abraham, "Analog testing with time response parameters," IEEE Design and Test of Computers, pp.18-25, vol. 13, 1996.
7. P.N.Variyam and A.Chatterjee, "Test Generation for comprehensive testing of linear analog circuits using transient response sampling," Intl. Conf. on Computer Aided Design, pp.382-385, 1997
8. P.N.Variyam and A.Chatterjee, "Enhancing Test Effectiveness for Analog Circuits using Synthesized Measurements," VLSI Test Symp., pp.132-137, 1998.
9. R.Voorakaranam and A.Chatterjee, "Test Generation for Accurate Prediction of Analog Specifications," VLSI Test Symp., pp.137-142, 2000.
10. J.H.Friedman, "Multivariate Adaptive Regression Splines," The Annals of Statistics, Vol. 19, No.11-141.