Synthesis of high performance low power PTL circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 209-212

  Samanta, D ^a   Dharmadeep, M C ^a   Pal, A ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; RECONFIGURABLE HARDWARE;

CIRCUIT REALIZATION; CIRCUIT SYNTHESIS; CMOS CIRCUITS; CMOS LOGIC; DEVELOPED MODEL; LOW-POWER CIRCUIT; STANDARD CELL; TECHNOLOGY MAPPING;

LOW POWER ELECTRONICS;

EID: 84943267799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195018     Document Type: Conference Paper

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