Recursive filtering on SIMD architectures

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2003-January, Issue , 2003, Pages 263-268

  Schaffer, R ^a   Hosemann, M ^a   Merker, R ^a   Fettweis, G ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Computer architecture; Digital filters; Digital signal processing; Digital signal processors; Filtering; Hardware; IIR filters; Partitioning algorithms; Process control; Signal processing algorithms

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; FILTRATION; HARDWARE; IIR FILTERS; IMPULSE RESPONSE; INTEGRATED CIRCUIT DESIGN; PARALLEL PROCESSING SYSTEMS; PROCESS CONTROL;

DIGITAL SIGNAL PROCESSORS (DSP); INFINITE IMPULSE RESPONSE; MULTIPLE PROCESSORS; PARTITIONING ALGORITHMS; RECURSIVE ALGORITHMS; RECURSIVE FILTERING; SIGNAL PROCESSING ALGORITHMS; SINGLE INSTRUCTION MULTIPLE DATA PARADIGMS;

SIGNAL PROCESSING;

EID: 84943229904     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235680     Document Type: Conference Paper

References (12)

1. T. Richter, W. Drescher, F. Engel, S. Kobayashi, V. Nikolajevic, and G. Fettweis, "A Platform-Based Highly Parallel Digital Signal Processor," in Proceedings of CICC, 2001.
2. J. Teich, A compiler for application specific processor arrays, Ph.D. thesis, Verlag Shaker, Aachen, Germany, 1993.
3. V. Roychowdhury, L. Thiele, S.K. Rao, and T. Kailath, "On the localisation of algorithms for VLSI processor arrays," VLSI Signal Processing III, pp. 459-470, 1989.
4. U. Eckhardt and R. Merker, "Hierarchical algorithm partitioning at system level for an improved utilization of memory structures," IEEE Transactions on CAD, vol. 18, no. 1, pp. 14-24, Jan. 2000.
5. J. Rosseel, F. Catthoor, and H. De Man, "An optimisation methodology for array mapping of affine recurrence equations in video and image processing applications," in Proc. Conf. on Appl.-Spec. Array Proc., Aug. 1994.
6. Matthias Weiss, Frank Engel, and Gerhard P. Fettweis, "A New Scalable DSP Architecture for System on Chip (SOC) Domain," in Proceedings of ICASSP'99, Phoenix, AZ, April 1999, vol. 4, pp. 1945-1948.
7. R.M. Karp, R.E. Miller, and S. Winograd, The organization of computation for uniform recurrence equations, J.ACM, July 1967.
8. S.K. Rao, Regular Iterative Algorithms and their Implementations on Processor Arrays, Ph.D. thesis, Stanford Univ., 1985.
9. U. Eckhardt, Algorithmus-Architektur-Codesign für den Entwurf digitaler Systeme mit eingebettetem Prozessorarray und Speicherhierarchie, Ph.D. thesis, Dresden University of Technology, Germany, June 2001.
10. K. Wang, Advanced Computer Architecture: Parallelism, Scalability, Programming, McGraw-Hill, New York, 1993.
11. J. Teich and L. Thiele, "Partitioning of processor arrays: A piecewise regular approach.," INTEGRATION: The VLSI Journal, vol. 14(3), pp. 297-332, 1993.
12. U. Eckhardt and R. Merker, "Co-partitioning - A method for hardware / software codesign for scalable systolic arrays," in Reconfigurable Architectures, R. Hartenstein and V. Prasanna, Eds., pp. 131-138. IT Press, Chicago, 1997.