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Volumn , Issue , 2003, Pages 243-248

Cluster growth revisited: Fast, mixed-signal placement of blocks and gates

Author keywords

Circuit simulation; Clustering algorithms; Cost function; Heuristic algorithms; Integrated circuit interconnections; Iterative algorithms; Macrocell networks; Routing; Signal design; Simulated annealing

Indexed keywords

ALGORITHMS; ASPECT RATIO; CIRCUIT SIMULATION; COST FUNCTIONS; COSTS; HEURISTIC ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT INTERCONNECTS; ITERATIVE METHODS; MIXED SIGNAL INTEGRATED CIRCUITS; SIMULATED ANNEALING;

EID: 84942531856     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2003.1190435     Document Type: Conference Paper
Times cited : (2)

References (18)
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    • NCSU Collaborative Benchmark Laboratory. WWW: http://www.cbl.ncsu.edu/pub/Benchmark-dirs/LayoutSynth92
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    • Block placement with symmetry constraints based on the O-tree non-slicing representation
    • Pang, Y., F. Balasa, et al. Block placement with symmetry constraints based on the O-tree non-slicing representation. Proceedings of the 2000 Design Automation Conference, pp: 64-467.
    • Proceedings of the 2000 Design Automation Conference , pp. 64-467
    • Pang, Y.1    Balasa, F.2
  • 12
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    • Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing
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    • 25th ACM/IEEE Design Automation Conference, 1988 , pp. 73-80
    • Sechen, C.1
  • 13
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    • June
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    • Shahookar, K.1    Mazumdar, P.2
  • 17
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    • Global Placement for VLSI Standard Cell Design
    • Submitted to
    • Yang, Z. and S. Areibi. Global Placement for VLSI Standard Cell Design. http://wolfman.eos.uoguelph.ca/~sareibi/PUBLICATIONS-dr/docs/CAINE-02-paper-place-initial.pdf. Submitted to CAINE 2002.
    • CAINE 2002
    • Yang, Z.1    Areibi, S.2
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    • Zhang, S., L. Wu, and W. Dai. WWW: http://www.cse.ucsc.edu/research/surf/GSRC/progress.html
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.