Adaptive cluster growth (ACG); A new algorithm for circuit packing in rectilinear region

Proceedings of the European Design Automation Conference, EDAC 1990

Volumn , Issue , 1990, Pages 191-195

  Kyung, C M ^a   Widder, J M ^b   Mlynski, D A ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; TIMING CIRCUITS;

ADAPTIVE CLUSTERS; BENCHMARK DATA; CHIP BOUNDARIES; CIRCUIT MODULES; GLOBAL PLACEMENTS; PACKING TECHNIQUES; REGION BOUNDARIES; ROUTING LENGTH;

CLUSTERING ALGORITHMS;

EID: 79958209895     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAC.1990.136643     Document Type: Conference Paper

References (27)

1. S.Sahni and A.Bhatt, "The complexity of design automation problems", Proc. 17th Design Automation Conference, pp.402-441, June 1980.
2. W.E. Donath, "Complexity Theory and design automation", Proc. 17th DAC, pp.412-419, June 1980.
3. M.A. Breuer, "Min-cut placement", J.Design Automation and Fault Tolerant Computing, vol. l, pp.343-382, Oct.l977.
4. A.E. Dunlop and B.W.Kernighan, "A procedure for placement of standard-ceU VLSI circuits", IEEE Trans, on CAD of IC's and Systems, vol. CAD-4, pp.92-98, Jan.l985.
5. B.W. Kernighan and S. Lin, "An effective heuristic for partitioning graphs", BSTJ, vol.49, pp. 291-307, Feb. 1970.
6. M.C. Chi, "An automatic rectilinear partitioning procedure for standard cells", Proc. 24th DAC, pp. 50-55, 1987.
7. T. Ohtsuki, "Minimum dissection of rectilinear region", Proc. IS-CAS, pp. 1210-1213, 1982.
8. N.R. Quinn and M.A. Breuer, "A force directed component placement procedure for printed circuit boards", IEEE Transactions on Circuits and Systems, vol. CAS-26, pp. 377-388, 1979.
9. C.K. Cheng and E.S. Kuh, "Module placement based on resistive network optimization", IEEE Trans, on CAD of IC's and Systems, vol. CAD-3, No.3, pp. 218-225, July 1984
10. R.S. Tsay, E.S. Kuh and C.P. Hsu, "Module placement for large chips based on sparse linear equations", Int. J. Circuit Theory and Applications, vol. 16, pp. 416-423, 1988.
11. J.P. Blanks, "Near-optimal placement using a quadratic objective function", Proc. 22nd DAC, pp.609-615, 1985.
12. J. Frankle and R.M. Karp, "Circuit placement and cost bound by eigenvector decomposition", Proc. ICCAD, pp. 414-417, 1986.
13. J.M. Kleinhans, G.Sigl and F.M. Johannes, "GORDIAN: A new global optimization/rectangl dissection method fo.-cell placement", Proc ICCAD, pp. 506-509, 1988.
14. G.J. Wipfler, M. Wiesel and D.A. Mlynski, "A combined force and cut algorithm for hierarchical VLSI layout", PROC. 19th DAC, pp. 671-676, 1982.
15. K.M.Just, J.M. Kleinhans and P.M. Johannes, "On the relative placement and the transportation problem for standard-cell layout", Proc. 23rd DAC, pp. 308-313, 1986.
16. L. Sha and R.W. Dutton, "An analytical algorith for placement of arbitrary sized rectangular blocks", Proc. 22nd DAC, pp. 602-608, 1985.
17. W.M. Dai and E.S. Kuh, "Hierarchical floor planning for building block layout", Proc. ICCAD, pp. 454-457, 1986.
18. P.R. Suaris and G. Kedem, "A quadrisection-based combined place and rout scheme for standart cells", IEEE Trans, on IC's and Systems, vol. CAD-8, No.3, pp. 234-244, March 1989.
19. K. Maling, S.H.Mueller and W.R. Heller, "On finding most optimal rectangular package plans", Proc. 19th DAC, pp. 663-670, 1982.
20. D.P. La Potin and S.W. Director, "Mason: A global floorplanning approach for VLSI design", IEEE Trans, on IC's and Systems, vol. CAD-5, No.4, pp. 477-489, Oct 1986.
21. D.F. Wong and C.L. Liu, "A new algorithm for floorplan design", Proc. 23rd DAC, pp. 101-107, 1986.
22. H. Shin and A. Sangiovanni-Vincentelli, "Two-dimensional com-pactation by zone refining", Proc. 23rd DAC, pp. 115-122, 1986.
23. I.C. Park CM. Kyung Cicuit placement in rectilinear region using graph matching" (in preparation).
24. S. Kirkpatrick, CD. Gelatt and M.P. Vecchi, "Optimization by simulated annealing", Science, vol. 220, pp. 671-680, May 1983.
25. C. Sechen and A. Sangiovanni-Vincentelli, "TimberWolf 3.2: A new standard-cell placement and global routing package", Proc. 23rd DAC, pp. 432-439, June 1986.
26. B. Preas, "Benchmarks for cell-based layout systems", Proc. 24th DAC, pp. 319-320, 1987.
27. CM.Fiduccia and R.M.Mattheyses, "A linear-time heuristic for improving network partitions", Proc. 19th DAC, pp. 175-181, 1982.