GFS: An efficient implementation of fair scheduling for multigigabit packet networks

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2003-January, Issue , 2003, Pages 389-399

  Kornaros, George ^a   Orphanoudakis, Theofanis ^a   Papaefstathiou, Ioannis ^a  

^a Ellemedia Tec Hnologies   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPLEX NETWORKS; COMPUTER ARCHITECTURE; NETWORK ARCHITECTURE; QUALITY OF SERVICE; SCHEDULING;

ASSOCIATED COSTS; CRITICAL FACTORS; EFFICIENT IMPLEMENTATION; NETWORK PROCESSING SYSTEMS; PACKET FAIR QUEUEING; PACKET FORWARDING; QUALITY OF SERVICE GUARANTEES; VARIABLE LENGTH PACKET;

SCHEDULING ALGORITHMS;

EID: 84942525858     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2003.1212862     Document Type: Conference Paper

References (17)

1. G. Kornaros. C. Kozyrakis, P.V atsolaki and M. Kate-enis, "Pipelined Multi-Queue Man agement in a VLSI A TMSwitch Chip with Credit-Based Flow-Control", 17th Con ference on Advanced Research in VLSI, University of Michigan, Ann Arbor, MI, USA. September 1997.
2. G. Kornaros et al, "ATLAS I: Implementing a Single-Chip Atm Switch with Backpressure", IEEE Micro, pp. 30-41, January 1999.
3. P. Guptaand N. McKeown, "Designing and Implementing a Fast Crossbar Scheduler", IEEE Micro, pp. 20-28, January 1999.
4. A.K. Parekh and R.G. Gallager, "A generalized processor sharing approach to flow control in integrated services net w ork:The single node case", IEEE/ACM T nns actions on Networking, vol. 1, pp. 344-357 June 1993.
5. A.K. Parekh and R.G. Gallager, "A generalized processor sharing approach to flow control in integrated services netw ork: The multiple node case", IEEE/A CM Transactions on Networking, pp. 137-150 April 1994.
6. J. Bennett and H. Zhang, "WF2Q: Worst-case fair weighted fair queueing", Pr oceedings IEEE INFOCOM, pp. 120-128, San Francisco, March 1996.
7. G. Kornaros, F. Orphanoudakis and I. Papaefstathiou, "Active Flow Identifiers for scalable, QoS scheduling in 10-Gbps netw ork processors", to appear in IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 2003.
8. J. Bennett and H. Zhang, "Hierarchical packet fair queueing algorithms", IEEE/ACM T ransactionson Networking, vol. 5, no. 5, pp. 675-689, October 1997.
9. J. Bennett, D. Stephens and H. Zhang, "High Speed, Scalable, and Accurate Implementation of Packet Fair Queueing Algorithms in ATM Netw orks", IEEE ICNP'97, Atlanta, USA, October 1997.
10. S. Zeng and N. Uzun, "A Hierarchical Traffic Shaper for Packet Switches", Globecom 1999, Rio de Janeiro, Brazil, December 1999.
11. J. Rexford, F. Bonomi, A. Greenberg and A. Wong, "Scalable Architectures for In tegrated T rafficShaping and Link Schedulingin High-Speed ATM Switches", IEEE journal on Selected Areas in Communications, pp. 938-950, June 1997.
12. I. Lepe, J. Garcia, "I/O bus usage control in PC-based software routers", IFIP Networking, Pisa, 2002.
13. Motorola Q-5 Product Sheet, http://e-www.motorola.com/webapp/sps/library/prod.lib.jsp
14. Cisco VIP4-80, http://www.cisco.com/univeicd/cc/td/doc/pcat/index.htm
15. EzChip, NP-1 netw ork protocol Data Sheet, http://www.ezchip.com/html/in-prod.html
16. Xebeo MetroBridge, Product Description, http://www.xebeo.com/solutions-products.htm
17. T. Orphanoudakis, G. Kornaros, LP apaefstathiou, H. Leligou, S. Perissakis, N. Zervos, "Scheduling components for multi-gigabit net w orkSoCs", SPIE's First International Symposium on Microtechnologies for the New Millennium-VLSI Circuits and Systems (EMT102), Maspalomas, Gran Canaria (Canary Islands), Spain, May 2003.