Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control

Proceedings of the Conference on Advanced Research in VLSI

Volumn , Issue , 1997, Pages 127-144

  Kornaros, George ^a   Kozyrakis, Christoforos ^a   Vatsolaki, Panagiota ^a   Katevenis, Manolis ^a  

^a Foundation for Research and Technology Hellas Science and Technology Park of Crete   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; BUFFER STORAGE; CELLULAR ARRAYS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; QUEUEING THEORY; RANDOM ACCESS STORAGE; SWITCHING NETWORKS; TIMING CIRCUITS; TRANSISTORS;

CREDIT BASED FLOW CONTROL; STATIC RANDOM ACCESS MEMORY (SRAM);

VLSI CIRCUITS;

EID: 0031386772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)