Active flow identifiers for scalable, QOS scheduling in 10-GBPS network processors

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Kornaros, George ^a   Orphanoudakis, Theofanis ^a   Papaefstathiou, Yannis ^b  

^a Ellemedia Technologies   (Greece)

^b INSTITUTE OF COMPUTER SCIENCE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; HARDWARE; LOGIC GATES; QUALITY OF SERVICE; SCHEDULING; TELECOMMUNICATION TRAFFIC;

NETWORK PROCESSORS;

COMPUTER NETWORKS;

EID: 0038760868     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. P.Gupta & N.McKeown. "Designing and Implementing a Fast Crossbar Scheduler" IEEE Micro, pp. 20-28, Jan 1999.
3. A.Ioannou and M.Katevenis. "Pipelined Heap (priority queue) Management for Advanced Scheduling in High Speed Networks" IEEE Int. Conf. on Communications (ICC'2001), Helsinki, Finland, Jun 2001.
4. J.Bennett, D.Stephens & H.Zhang. "High Speed, Scalable, and Accurate Implementation of Packet Fair Queueing Algorithms in Atm Networks" IEEE ICNP'97, Atlanta, USA, Oct 1997.
5. G.Kornaros et al "ATLAS I; Implementing a Single-Chip Atm Switch with Backpressure" IEEE Micro, pp. 30-41, Jan 1999.
6. T.Chaney, J.Fingerhut, M.Flucke and J.Turner. "Design of a gigabit ATM switch" INFOCOM, Kobe, Japan, Apr 1997.
7. R.Krishnamurthy et al "Architecture and Hardware for Scheduling Gigabit Packet Streams" 10th Hot Interconnects, Stanford, California, Aug 2002.