Power dissipation reductions with genetic algorithms

Proceedings - NASA/DoD Conference on Evolvable Hardware, EH

Volumn 2003-January, Issue , 2003, Pages 111-116

  Takahashi, E ^a   Murakawa, M ^a   Kasai, Y ^a   Higuchi, T ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

Cellular phones; Circuit testing; Clocks; Delay; Energy consumption; Filters; Genetic algorithms; Large scale integration; Power dissipation; Timing

Indexed keywords

ALGORITHMS; CELLULAR TELEPHONES; CLOCKS; ENERGY DISSIPATION; ENERGY UTILIZATION; FILTERS (FOR FLUIDS); GENETIC ALGORITHMS; HARDWARE; INTEGRATION TESTING; LSI CIRCUITS; MOBILE PHONES; NASA; TELEPHONE CIRCUITS; TELEPHONE SETS; TIMING CIRCUITS;

CELLULAR PHONE; CIRCUIT PARAMETER; CIRCUIT TESTING; CLOCK-TIMING ADJUSTMENT; DELAY; INTERMEDIATE FREQUENCIES; POWER DISSIPATION REDUCTION; TIMING;

ELECTRIC LOSSES;

EID: 84942415648     PISSN: 15506029     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.2003.1217654     Document Type: Conference Paper

References (7)

1. E. Takahashi, Y. Kasai, M. Murakawa, T. Higuchi, "A Post-Silicon Clock Timing Adjustment Using Genetic Algorithms", 2003 Symposium on VLSI Circuits Digest of Technical Papers, June 2003.
2. M. Murakawa, T. Adachi, Y. Niino, Y. Kasai, E. Takahashi, K. Takasuka, T. Higuchi, "An AI-Calibrated IF Filter: A Yield Enhancement Method With Area and Power Dissipation Reductions", IEEE Journal of Solid-State Circuits, vol.38, no. 3, pp. 495-502, March 2003.
3. E. Takahashi, M. Murakawa, K. Toda, T. Higuchi, "An Evolvable-Hardware-based Clock Architecture towards GigaHz Digital Systems," Proc. of AAAI GECCO'99(Genetic Algorithm and Evolutionary Computation Conference), pp.1204-1210, July 1999.
4. D. Deleganes, J. Douglas, B. Kommandaur, M. Patyra, "Design a 3GHz, 130nm, Pentium4 Processor," Proc. of 2002 Symposium on VLSI Circuits, Feb. 2002.
5. T. Higuchi, et al. "Real-World Applications of Analog and Digital Evolvable Hardware," IEEE Transactions of Evolutionary Computation, vol.3, pp. 220-235, 1999.
6. T. Sakurai, "LSI design toward 2010 low-power technology," International Conference on VLSI & CAD '99, pp.325-334, Oct. 1999.
7. T. Adachi, A. Ishikawa, K. Tomioka, S. Hara, K. Takasuka, H. Hisajima, and A. Barlow. "A low noise integrated AMPs if filter", Proceedings of the IEEE 1994 Custom Integrated Circuits Conference, pp. 159-162, 1994.