A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 336-337

  Ju, Chi Cheng ^a   Liu, Tsu Ming ^a   Lee, Kun Bin ^a   Chang, Yung Chang ^a   Chou, Han Liang ^a   Wang, Chin Ming ^a   Wu, Tung Hsing ^a   Lin, Hue Min ^a   Huang, Yi Hsin ^a   Cheng, Chia Yun ^a   Lin, Ting An ^a   Chen, Chun Chia ^a   Lin, Yu Kun ^a   Chiu, Min Hao ^a   Li, Wei Cing ^a   Wang, Sheng Jen ^a   Lai, Yen Chieh ^a   Chao, Ping ^a   Chien, Chih Da ^a   Hu, Meng Jye ^a   Wang, Peng Hao ^a   Yeh, Fu Chun ^a   Huang, Yen Chao ^a   Chuang, Shun Hsiang ^a   Chen, Lien Fei ^a   Lin, Hsiu Yi ^a   Wu, Ming Long ^a   Chen, Che Hong ^a   Chen, Ryan ^a   Hsu, H Y ^a   Jou, Kevin ^a   more..

^a MEDIATEK INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; ENCODING (SYMBOLS); LSI CIRCUITS; SIGNAL ENCODING; SMARTPHONES;

28NM CMOS; ENCODING AND DECODING; LSI CHIPS; OPTIMIZATIONS (RDO); REAL TIME; SINGLE CHIPS; SMART-PHONE APPLICATIONS; VIDEO CODECS;

MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 84940763564     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7063063     Document Type: Conference Paper

References (3)

1. C.-T. Huang, et al., "A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications, " ISSCC Dig. Tech. Papers, pp. 162-163, Feb. 2013.
2. C.-C. Ju, et al., " A 0.2nJ/pixel 4K 60fps Main-10 HEVC Decoder with Multi-format Capabilities for UHD-TV Applications, " European Solid-State Circuits Conf., pp. 195-198, 2014.
3. A. Wang, et al., "Heterogeneous Multi-Processing Quad-Core CPU and Dual-GPU Design for Optimal Performance, Power, and Thermal Tradeoffs in a 28nm Mobile Application Processor, " ISSCC Dig. Tech. Papers, pp. 180-181, Feb. 2014.