A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 464-465

  Sung, Ba Ro Saim ^a   Jo, Dong Shin ^a   Jang, Il Hoon ^a   Lee, Dong Suk ^b   You, Yong Sang ^b   Lee, Yong Hee ^b   Park, Ho Jin ^b   Ryu, Seung Tak ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; MEMORY ARCHITECTURE; TIMING CIRCUITS;

CALIBRATION SCHEMES; CIRCUIT COMPLEXITY; CONVERSION RATES; CONVERSION SPEED; TARGET SPEED; TIME-INTERLEAVED; TIME-INTERLEAVING; TIMING SKEW;

ANALOG TO DIGITAL CONVERSION;

EID: 84940762178     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7063127     Document Type: Conference Paper

References (4)

1. B. Sung, et al., "A 6 bit 2 GS/s Flash-Assisted Time-Interleaved (FATI) SAR ADC with Background Offset Calibration" Proc. IEEE A-SSCC, pp. 281-284, Nov. 2013.
2. S. Lee, et al., "A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration, " ISSCC Dig. Tech. Papers, pp. 384-385, Feb. 2014.
3. S. Cho, et al., "A 550-μW 10-b 40-MS/s SAR ADC with Multistep Addition-Only Digital Error Correction, " IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1881-1892, Aug. 2011.
4. M. El-Chammas, et al., "A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration, " IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Apr. 2011.