CUD@SAT: SAT solving on GPUs

Journal of Experimental and Theoretical Artificial Intelligence

Volumn 27, Issue 3, 2015, Pages 293-316

  Dal Palù, Alessandro ^a   Dovier, Agostino ^b   Formisano, Andrea ^c   Pontelli, Enrico ^d  

^a UNIVERSITY OF PARMA   (Italy)

^b UNIVERSITY OF UDINE   (Italy)

^c UNIVERSITY OF PERUGIA   (Italy)

^d New Mexico State University   (United States)

Author keywords

CNF satisfiability; Davis Putnam Logemann Loveland procedure; general purpose GPU computing; parallel SAT solving

Indexed keywords

FORMAL LOGIC; PROGRAM PROCESSORS; WELL TESTING;

CNF SATISFIABILITY; COMPUTE UNIFIED DEVICE ARCHITECTURES; DAVIS-PUTNAM-LOGEMANN-LOVELAND PROCEDURES; GENERAL-PURPOSE GPU COMPUTING; GRAPHIC PROCESSING UNITS (GPUS); PARALLEL COM- PUTING; SAT-SOLVING; SATISFIABILITY TESTING;

GRAPHICS PROCESSING UNIT;

EID: 84929177526     PISSN: 0952813X     EISSN: 13623079     Source Type: Journal    
DOI: 10.1080/0952813X.2014.954274     Document Type: Article

References (47)

1. Apt, K. (2009). Principles of constraint programming. Cambridge: Cambridge University Press.
2. Baral, C. (2010). Knowledge representation, reasoning and declarative problem solving. Cambridge: Cambridge University Press.
3. Bayardo, R., & Schrag, R. (1997). Using CSP look-back techniques to solve real-world SAT instances. In 14th national conference on artificial intelligence. Menlo Park, CA: AAAI Press.
4. Beckers, S., De Samblanx, G., De Smedt, F., Goedemé, T., Struyf, L., & Vennekens, J. (2011). Parallel SAT-solving with OpenCL. In H. Weghorn, L. Azevedo, & P. Isaias (Eds.), Proceedings of the IADIS international conference on applied computing (pp. 435-441). Lisbon: IADIS.
5. Bell, N., & Garland, M. (2008). Efficient sparse matrix-vector multiplication on CUDA. Tech. Rep. No. NVR-2008-004. Santa Clara, CA: NVIDIA Corporation.
6. Biere, A., Heule, M., van Maaren, H., & Walsh, T. (Eds.). (2009). Handbook of satisfiability (Vol. 185). Amsterdam: IOS Press.
7. Blochinger, W., Sinz, C., & Kuchlin, W. (2003). Parallel propositional satisfiability checking with distributed dynamic learning. Parallel Computing, 29, 969-994.
8. Bohm, M., & Speckenmeyer, E. (1996). A fast parallel SAT solver: Efficient workload balancing. Annals of Mathematics and Artificial Intelligence, 17, 381-400.
9. Campeotto, F., Dal Palù, A., Dovier, A., Fioretto, F., & Pontelli, E. (2014). Exploring the use of GPUs in constraint solving. In Proceedings of practical aspects of declarative languages (PADL). LNCS. (Vol. 8324, pp. 152-167). New York, NY: Springer.
10. Campeotto, F., Dovier, A., Fioretto, F., & Pontelli, E. (2014). A GPU implementation of large neighborhood search for solving constraint optimization problems. In Proceedings of 21st European conference on artificial intelligence (ECAI) (pp. 189-194). Amsterdam: IOS Press.
11. Campeotto, F., Dovier, A., & Pontelli, E. (2013). Protein structure prediction on GPU: A declarative approach in a multi-agent framework. In Proceedings of international conference on parallel processing (ICPP) (pp. 474-479). Washington, DC: IEEE Press.
12. Cecilia, J., Garcia, J., Guerrero, G., del Amor, M. M., Perez-Hurtado, I., & Perez-Jimenez, M. (2010). Simulating a P system based efficient solution to SAT by using GPUs. The Journal of Logic and Algebraic Programming, 79, 317-325.
13. Chakroun, I., Mezmaz, M.-S., Melab, N., & Bendjoudi, A. (2013). Reducing thread divergence in a GPUaccelerated branch-and-bound algorithm. Concurrency and Computation: Practice and Experience, 25, 1121-1136.
14. Chrabakh, W., & Wolski, R. (2003). GrADSAT: A parallel SAT solver for the GRID. Tech. Rep. No. 2003- 05. Santa Clara, CA: University of California.
15. Chu, G., Stuckey, P., & Harwood, A. (2008). pMiniSat: A parallelization of MiniSat 2.0. Tech. Rep. Guangzhou: SAT-Race System Descriptions, Affiliated with SAT'08.
16. Claessen, K., Een, N., Sheeran, M., Sorensson, N., Voronov, A., & Akesson, K. (2009). SAT-Solving in Practice SAT-solving in practice. Discrete Event Dynamic Systems, 19, 495-524.
17. Dal Palù, A., Dovier, A., Formisano, A., & Pontelli, E. (2012). Exploiting unexploited computing resources for computational logics. In Proceedings of the 9th Italian convention on computational logic (Vol. 857, pp. 74-88). Aachen: CEUR-WS.org.
18. Davis, M., Logemann, G., & Loveland, D. (1962). A machine program for theorem proving. Communications of the ACM, 5, 394-397.
19. Diamos, G. F., Ashbaugh, B., Maiyuran, S., Kerr, A., Wu, H., & Yalamanchili, S. (2011). SIMD reconvergence at thread frontiers. In Proceedings of the 44th annual IEEE/ACM international symposium on microarchitecture (pp. 477-488). New York, NY: ACM Press.
20. Eén, N., & Sörensson, N. (2004). An extensible SAT-solver. In Theory and applications of satisfiability testing (pp. 502-518). New York, NY: Springer.
21. Feldman, Y., Deshowitz, N., & Hanna, Z. (2004). Parallel multithreaded satisfiability solver: Design and implementation. In Proceedings of the 3rd international workshop on parallel and distributed methods in verification (PDMC) (Vol. 128, pp. 75-90). Philadelphia, PA: Elsevier.
22. Fujii, H., & Fujimoto, N. (2012). GPU acceleration of BCP procedure for SAT algorithms. IPSJ SIG Notes, 2012, 1-6.
23. Gil, L., Flores, P., & Silveira, L. (2008). PMSat: A parallel version of MiniSat. Journal on Satisfiability, Boolean Modeling and Computation, 6, 71-98.
24. Gulati, K., & Khatri, S. P. (2010). Boolean satisfiability on a graphics processor. In Great lakes symposium on VLSI (pp. 123-126). New York, NY: ACM Press.
25. Hamadi, Y., Jabbour, S., & Sais, L. (2009). ManySAT: a parallel SAT solver. Journal on Satisfiability, Boolean Modeling and Computation, 6, 245-262.
26. Han, T. D., & Abdelrahman, T. S. (2011). Reducing branch divergence in GPU programs. In Processing units proceedings of the fourth workshop on general purpose processing on graphics processing units (pp. 31-38). New York, NY: ACM Press.
27. Henz, M., & Muller, T. (2000). An overview of finite domain constraint programming. In Proceedings of the fifth conference of the association of Asia-Pacific operational research societies. Singapore: APORS.
28. Holldobler, S., Manthey, N., Nguyen, V., Stecklina, J., & Steinke, P. (2011). A short overview on modern parallel SAT-solvers. In Advanced computer science and information system (ICACSIS) (pp. 201-206). Washington, DC: IEEE Computer Society.
29. Islam, S., Tandon, R., Singh, S., & Misra, A. (2011). A highly scalable solution of an NP-complete problem using CUDA. In Parallel computing in electrical engineering (PARELEC), 6th international symposium (pp. 93-98). Washington, DC: IEEE.
30. Jeroslow, R. G., & Wang, J. (1990). Solving propositional satisfiability problems. Annals of Mathematics and Artificial Intelligence, 1, 167-187.
31. Jurkowiak, B., Li, C., & Utard, G. (2001). Parallelizing Satz using dynamic workload balancing. Electronic Notes in Discrete Mathematics, 9, 174-189.
32. Jurkowiak, B., Li, C., & Utard, G. (2005). A parallelization scheme based on work stealing for a class of SAT solvers. Journal of Automated Reasoning, 34, 73-101.
33. Kirk, D. B., & Hwu, W. (2010). Programming massively parallel processors: A hands-on approach. Philadelphia, PA: Morgan Kaufmann.
34. Lewis, M., Schubert, T., & Becker, B. (2007). Multithreaded SAT solving multithreaded SAT solving. In 12th Asia and South Pacific design automation conference (pp. 926-931). Washington, DC: IEEE Computer Society.
35. Manolios, P., & Zhang, Y. (2006). Implementing survey propagation on graphics processing units. In Theory and applications of satisfiability testing (pp. 311-324). New York, NY: Springer.
36. Manthey, N. (2011). Parallel SAT solving - using more cores. Tech. Rep. No. KRR Report 11-02. Dresden: Technische Universität.
37. Marques Silva, J. P., & Sakallah, K. A. (1999). GRASP: A search algorithm for propositional satisfiability. IEEE Transactions on Computers, 48, 506-521.
38. Meyer, Q., Schonfeld, F., Stamminger, M., & Wanka, R. (2010). 3-SAT on CUDA: Towards a massively parallel SAT solver. In W. W. Smari & J. P. McIntire (Eds.), 2010 international conference on high performance computing and simulation (HPCS) (pp. 306-313). Washington, DC: IEEE Computer Society.
39. Munawar, A., Wahib, M., Munetomo, M., & Akama, K. (2009). Hybrid of genetic algorithm and local search to solve MAX-SAT problem using NVIDIA CUDA framework. Genetic Programming and Evolvable Machines, 10, 391-415.
40. Nickolls, J., & Dally, W. (2010). The GPU computing era. IEEE Micro, 30, 56-69.
41. NVIDIA. (2012). NVIDIA CUDA C: Programming guide, version 4.2. Santa Clara, CA: NVIDIA Press.
42. Owens, J., Houston, M., Luebke, D., Green, S., Stone, J., & Phillips, J. (2008). GPU computing. Proceedings of the IEEE, 96, 879-899.
43. Schubert, T., Lewis, M., & Becker, B. (2005). PaMira: A parallel SAT solver with knowledge sharing. In International workshop on microprocessor test and verification (MTV) (pp. 29-36). Washington, DC: IEEE.
44. Singer, D. (2007). Parallel resolution of the satisfiability problem: A survey. Tech. Rep. No. 2007-101 2007-101. Metz: Université Paul Verlaine.
45. Vella, F., Dal Palù, A., Dovier, A., Formisano, A., & Pontelli, E. (2013). CUD@ASP: Experimenting with GPGPUs in ASP solving. In Proceedings of the 28th Italian conference on computational logic (Vol. 1068, pp. 163-177). Aachen: CEUR-WS.org.
46. Zhang, H., Bonacina, M., & Hsiang, J. (1996). PSato: A distributed propositional prover and its application to quasigroup problems. Journal of Symbolic Computation, 21, 543-560.
47. Zhang, L., Madigan, C. F., Moskewicz, M. W., & Malik, S. (2001). Efficient conflict driven learning in Boolean satisfiability solver. In IEEE/ACM international conference on computer-aided design (pp. 279-285). Washington, DC: IEEE.