An 8-bit 100-gs/s distributed DAC in 28-nm CMOS for optical communications

IEEE Transactions on Microwave Theory and Techniques

Volumn 63, Issue 4, 2015, Pages 1211-1218

  Huang, Hao ^a   Heilmeyer, Johannes ^b   Grozing, Markus ^a   Berroth, Manfred ^a   Leibrich, Jochen ^c   Rosenkranz, Werner ^c  

^a UNIVERSITY OF STUTTGART   (Germany)

^b Advantest Europe GmbH   (Germany)

^c UNIVERSITY OF KIEL   (Germany)

Author keywords

Digital analog conversion; distributed amplifiers; filters

Indexed keywords

BROADBAND AMPLIFIERS; DIGITAL TO ANALOG CONVERSION; ELECTRIC POWER SYSTEMS; FILTERS (FOR FLUIDS); MICROPROCESSOR CHIPS; OPTICAL COMMUNICATION;

DESIGN FOR TEST; DISTRIBUTED AMPLIFIER; EFFECTIVE NUMBER OF BITS; MULTIPLE OUTPUTS; RETURN-TO-ZERO; SIGNAL FREQUENCIES; SPURIOUS FREE DYNAMIC RANGE; TRANSMISSION RATES;

DIGITAL INTEGRATED CIRCUITS;

EID: 84927669149     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2015.2403846     Document Type: Article

References (10)

1. C. Laperle and M. O'Sullivan, "Advances in high-speed DACs, ADCs, and DSP for optical coherent transceivers, " J. Lightw. Technol., vol. 32, no. 4, pp. 629-643, Feb. 2014.
2. Y. M. Greshishchev et al., "A 56 GS/S 6 b DAC in 65 nm CMOS with 256 6 b memory, " in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2011, pp. 194-196.
3. "Digital to analog converter-Factsheet LEIA 55-65 GSa/s 8-bit DAC, " Fujitsu Semicond. Europe, Langen, Germany, YEAR. [Online]. Available: http://www.fujitsu.com/downloads/MICRO/fme/documentation/c60.pdf
4. A. Balteanu, P. Schvan, and S. P. Voinigescu, "A 6-bit segmented RZ DAC architecture with up to 50-GHz sampling clock and 4 VPP differential swing, " in IEEE MTT-S. Int. Microw. Symp. Dig., 2012, pp. 1-3.
5. S. Randel et al., "Generation of a digitally shaped 55-GBd 64-QAM single-carrier signal using novel high-speed DACs, " in Proc. Opt. Fiber Commun. Conf. Exhibit., 2014, pp. 1-3.
6. T. Alpert, F. Lang, D. Ferenci, M. Grözing, and M. Berroth, "A 28 GS/s 6 b pseudo segmented current steering DAC in 90 nm CMOS, " in IEEE MTT-S. Int. Microw. Symp. Dig., 2011, pp. 1-4.
7. J. Savoj, A. Abbasfar, A. Amirkhany, M. Jeeradit, and B. W. Garlepp, "A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications, " IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1207-1216, May 2008.
8. J. Deveugele, P. Palmers, and M. Steyaert, "Parallel-path digital-toanalog converters for Nyquist signal generation, " IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1073-1082, Jul. 2004.
9. H. Huang, J. Heilmeyer, M. Grözing, and M. Berroth, "An 8-bit 100-GS/s distributed DAC in 28-nm CMOS, " in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2014, pp. 65-68.
10. K. Myounggon, J. Gil, and S. Hyungcheol, "A simple parameter extraction method of spiral on-chip inductors, " IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1976-1981, Sep. 2005.