Advances in high-speed DACs, ADCs, and DSP for optical coherent transceivers

Journal of Lightwave Technology

Volumn 32, Issue 4, 2014, Pages 629-643

  Laperle, Charles ^a   Osullivan, Maurice ^a  

^a Signal Integrity   (Canada)

Author keywords

Analog digital conversion; digital signal processing; digital analog conversion; optical coherent transceivers; optical fiber communication

Indexed keywords

ANALOG-DIGITAL CONVERSION; ANALOG-TO-DIGITAL; COHERENT TRANSCEIVER; DIGITAL SIGNAL PROCESSING (DSP); DIGITAL-ANALOG CONVERSION; DIGITAL-TO-ANALOG CONVERTERS;

DIGITAL SIGNAL PROCESSING; OPTICAL FIBER COMMUNICATION; TRANSCEIVERS;

OPTICAL TRANSCEIVERS;

EID: 84893405649     PISSN: 07338724     EISSN: None     Source Type: Journal    
DOI: 10.1109/JLT.2013.2284134     Document Type: Article

References (54)

1. Cisco. Cisco Visual Networking Index: Forecast and Methodology, 2012-2017. (May 2013). [Online]. Available: http://www.cisco.com/en/US/ solutions/collateral/ns341/ns525/ns537/ns705/ns827/white-paper-c11-481360.pdf
2. J.McNicol et al., "Electrical domain compensation of optical dispersion," presented at the Optical FiberCommunication Conf., Anaheim,CA, USA, 2005, paper OThJ3.
3. H. Sun, K.-T.Wu, and K. Roberts, "Real-time measurements of a 40 Gb/s coherent system," Opt (Pubitemid 351162223)
4. T. Ellermeyer et al., "DA and AD converters in SiGe technology : Speed and resolution for ultra high data rate applications," presented at the Eur. Conf. Optical Communication, Torino, Italy, 2010, paper Th.10.A.6.
5. W. Kester. Basic DAC architectures I: string DACs and thermometer (fully decoded)DACs. (Oct. 2008). [Online].Available: http://www.analog.com/static/ imported-files/tutorials/MT-014.pdf
6. W. Kester. Basic DAC architectures II: binary DACs. (Oct. 2008). [Online]. Available: http://www.analog.com/static/importedfiles/tutorials/MT- 015.pdf
7. W. Kester, "Basic DAC architectures III: segmented DACs," (Oct. 2008). [Online]. Available: http://www.analog.com/static/imported-files/ tutorials/MT-016.pdf.
8. T. A. Schaffer et al., "A 2 GHz 12-bit digital-to-analog converter for direct digital synthesis applications," in Proc. Gallium Arsenide Integr. Circuits Symp., Orlando, FL, USA, 1996, pp. 61-64.
9. W. Kester. Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR soYouDon't Get Lost in theNoise Floor. (Oct. 2008). [Online].Available: http://www.analog.com/static/imported-files/tutorials/MT-003.pdf
10. W. Kester. Taking the mystery out of the infamous formula, "SNR= 6.02 N + 1.76dB," and why you should care. (Oct. 2008). [Online]. Available: http://www.analog.com/static/imported-files/tutorials/MT-001.pdf
11. P. Schvan, D. Pollex, and T. Bellingrath, "A 22 GS/s 6b DAC with integrated digital ramp generator," in Proc. Int. Solid-State Circ. Conf. Dig. Tech. Papers, San Francisco, CA, USA, 2005, pp. 122-123.
12. Y. M. Greshishchev et al., "A 56 GS/s 6b DAC in 65 nm CMOS with 256×6b memory," in Proc. Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, USA, 2011, pp. 194-196.
13. D. Baranauskas and D. Zelenin, "A 0.36 W up to 20 GS/s DAC for UWB wave formation," in Proc. Int. Solid-State Circuits Conf.Dig. Tech. Papers, San Francisco, CA, USA, 2006, pp. 2380-2389.
14. M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, "Ultrahigh-speed low-power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems," IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2215-2225, Oct. 2011.
15. M. Nagatani et al., "A 32-GS/s 6-bit double-sampling DAC in InP HBT technology," in Proc. IEEE Compound Semicond. Integr. Circuits Symp., Greensboro, NC, USA, 2009, pp. 1-4.
16. Micram. VEGA I and II, Up to 34 GS/s, 6-bit ultrafast digital to analog converters. (2009). [Online]. Available: http://www.micram.com/attachments/030- VEGA%20DAC%20Family[1].pdf
17. T. Sugihara et al., "43 Gb/s DQPSK pre-equalization employing 6-bit, 43 GS/s DAC integrated LSI for cascaded ROADM filtering," presented at the Optical Fiber Conf., San Diego, CA, USA, 2010, paper PDPB6.
18. M. Nagatani et al., "A 60-GS/s 6-bit DAC in 0.5?m InP HBT technology for optical communication systems," in Proc.Compound Semicond. Integr. Circuits Symp., Waikoloa, HI, USA, 2011, pp. 1-4.
19. S. Halder et al., "A 20 GS/s 8-bit current steering DAC in 0.25?m SiGe BiCMOS technology," in Proc. Eur. Microw. Integr. Circuits Conf., Amsterdam, The Netherlands, 2008, pp. 147-150.
20. Fujitsu. Digital to analog converter. (Mar. 2012). [Online]. Available: http://www.fujitsu.com/downloads/MICRO/fme/documentation/c60.pdf
21. Tektronix. Tektronix announces world's fastest 10-bit commercial DAC. (Mar. 2013). [Online]. Available: http://component-solutions.tek.com/news- library/Tektronix%20Component%20Solutions%20Announces% 20Worlds%20Fastest%2010- bit%20Commercial%20DAC%20-%20031 813.pdf.
22. Waveform Generators Run To 50 GSamples/s. (Apr. 2013). [Online]. Available: http://defenseelectronicsmag.com/test-ampmeasurement/waveform- generators-run-50-gsampless
23. P. Schvan et al., "A 24 GS/s 6b ADC in 90 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 544-545.
24. Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000, 2001.
25. Y. M. Greshishchev et al., "A 40 GS/s 6b ADC in 65 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, USA, 2010, pp. 390-391.
26. S. Shahramian, S. P. Voinigescu, and A.C. Carusone, "A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1709-1720, Jun. 2009.
27. M. Chu, P. Jacob, J.-W. Kim, M. R. LeRoy, R. P. Kraft, and J. F. McDonald, "A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology," IEEE. J. Solid-State Circuits, vol. 45, no. 2, pp. 380-390, Feb. 2010.
28. P. Schvan et al., "A 22 GS/s 5b ADC in 0.13?m SiGe BiCMOS," in Proc. Int. Solid-State Circuits Conf.Dig. Tech. Papers, San Francisco, CA, USA, 2006, pp. 572-573.
29. J. Lee et al., "A 24 GS/s 5-b ADC with closed-loop THA in 0.18 m SiGe BiCMOS," in Proc. IEEE Custom Integr. Circuits Conf., 2008, pp. 313-316.
30. R. A. Kertis et al., "A 35 GS/s 5-Bit SiGe BiCMOS flash ADC with offset corrected exclusive-or comparator," in Proc. Bipolar/BiCMOS Circuits Technol. Meet., 2008, pp. 252-255.
31. R. A. Kertis, J. S. Humble, M. A. Daun-Lindberg, R. A. Philpott, K. E. Fritz, D. J. Schwab, J. F. Prairie, B. K. Gilbert, and E. S. Daniel, "A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators," IEEE. J. Solid-State Circuits, vol. 44, no. 9, pp. 2295-2311, Sep. 2009.
32. Micram. VEGA ADC30, 30 GS/s, 6-bit ultrafast analog to digital converter. (2009). [Online]. Available: http://www.micram.com/attachments/030- VEGA%20ADC30%20two-page.pdf
33. K. Poulton et al., "A 20 GS/s 8b ADC with a 1MB Memory in 0.18?m CMOS," in Proc. Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, USA, 2003, pp. 318-319.
34. I. Dedic, "56 GS/s ADC: Enabling 100GbE," presented at the Optical Fiber Communication Conf., San Diego, CA, USA, 2010, paper OThT6.
35. Fujitsu. Fujitsu Demonstrates First ADC Device in Family of 28 nm CMOSConverter Solutions. (Mar. 2013). [Online].Available: http://www. fujitsu.com/emea/news/pr/fseu-en-20130312-1054-fujitsu-adc-28 nmcmos-converter.html
36. R. H. Walden, "Performance trends for analog-to-digital converters," IEEE Commun. Mag., vol. 37, no. 2, pp. 96-101, Feb. 1999.
37. B. Murmann. ADC performance survey 1997-2013. (Jun. 2013). [Online]. Available: http://www.stanford.edu/?murmann/adcsurvey.html
38. A. Khilo et al., "Photonic ADC : overcoming the bottleneck of electronic jitter," Opt. Exp., vol. 20, no. 4, pp. 4454-4469, Feb. 2012.
39. W. Kester. Aperture time, aperture, jitter, aperture delay time-Removing the confusion. (Oct. 2008). [Online]. Available: http://www.analog.com/static/ imported-files/tutorials/MT-007.pdf
40. P. J. Pupalaikis andM. Schnecker, "A 30 GHz bandwidth, 80 GS/s sample rate real-time waveform digitizing system," presented at the Optical Fiber Communication Conf., San Diego, CA, USA, 2010, paper JThA52.
41. B. Spinnler, "Equalizer design and complexity for digital coherent receivers," IEEE J. Sel. Topics Quantum Electron., vol. 16, no. 5, pp. 1180-1192, Sep./Oct. 2010.
42. R. Kudo, T. Kobayashi, K. Ishihara, Y. Takatori, A. Sano, and Y. Miyamoto, "Coherent optical single carrier transmission using overlap frequency domain equalization for long-haul optical systems," J. Lightw. Technol., vol. 27, no. 16, pp. 3721-3728, Aug. 2009.
43. A. Mecozzi, C. B. Clausen, and M. Shtaif, "Analysis of intrachannel nonlinear effects in highly dispersed optical pulse transmission," IEEE Photon. Technol. Lett., vol. 12, no. 4, pp. 392-394, Apr. 2000.
44. J. Gaudette and J.Hopkins, "Optimizing optical pre-dispersion using transmit DSP for mitigation of Kerr nonlinearities in dispersion managed cables," presented at the Photonics North, Ottawa, ON, Canada, 2013, paper OP-COMM-2-12-3.
45. B. Cĥatelain et al., "A family of Nyquist pulses for coherent optical communications," Opt. Exp., vol. 20, no. 8, pp. 8397-8416, Apr. 2012.
46. BT and Ciena LightWorld's First 800G Super-Channel. (May 2013). [Online]. Available: http://www.ciena.com/about/newsroom/press-releases/BT-and-Ciena- Light-Worlds-First-800G-Super-Channel.html
47. R. Schmogrow, S. Ben-Ezra, P. C. Schindler, B. Nebendahl, C. Koos, W. Freude, and J. Leuthold, "Pulse-shaping with digital, electrical, and optical filters-A comparison," J. Lightw. Technol., vol. 31, no. 15, pp. 2570-2577, Aug. 2013.
48. M. G. Taylor, "Phase estimation methods for optical coherent detection using digital signal processing," J. Lightw. Technol., vol. 27, no. 7, pp. 901-914, Apr. 2009.
49. H. Zhang et al., "Cycle slip mitigation in POLMUX-QPSK modulation," presented at the Optical Fiber Communication Conf., Los Angeles, CA, USA, 2011, paper OMJ7.
50. J. Harley, K. Roberts, and H. Sun. (2012, April 24). Cycle slip location and correction, Patent 8166365B2. [Online]. Available: http://patft. uspto.gov/netacgi/nph-Parser?Sect2=PTO1= HITOFF=1 =/netahtml/PTO/search-bool. html=1= G=50=PALL Srch=yes=PN/8166365
51. F. Chang, K. Onohara, and T. Mizuochi, "Forward error correction for 100 G transport networks," IEEE Comm. Mag., vol. 48, no. 3, pp. S48-S55, Mar. 2010.
52. W. Kaiser et al., "Integrated circuits for coherent transceivers for 100 G and beyond," Opt. Fiber Technol., vol. 17, pp. 456-463, 2011.
53. D. Crivelli et al., "A 40 nm CMOS single-chip 50 Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels," in Proc. Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, USA, 2012, pp. 328-330.
54. K. Grobe et al., "Software-defined optics as solution for next-generation inter-data-center ultra-high-speedDWDMtransport," presented at the Terena Networking Conf., Reykjavik, Iceland, 2012.