SCOPUS 정보 검색 플랫폼

Volumn 2001-January, Issue , 2001, Pages 12-21

5-V tolerant fail-safe ESD solutions for 0.18μm logic CMOS process

Author keywords

Capacitance; CMOS logic circuits; CMOS process; CMOS technology; Electrostatic discharge; Low voltage; Protection; Rails; Thyristors; Transistors

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DISCHARGE; LOGIC CIRCUITS; RAILS; THYRISTORS; TRANSISTORS; VOLTAGE CONTROL;

CMOS LOGIC CIRCUITS; CMOS PROCESSS; CMOS TECHNOLOGY; LOW VOLTAGES; PROTECTION;

ELECTROSTATIC DEVICES;

EID: 84948974624 PISSN: 07395159 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (8)

References (8)

1
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- Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions
- M. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker, and W. Fichtber, Analysis and Compact Modeling of Lateral DMOS Power Devices Under ESD Stress Conditions, ESD Symp. Proc., pp1-10, 1999
- (1999) ESD Symp. Proc , pp. 1-10
- Mergens, M.¹ Wilkening, W.² Mettler, S.³ Wolf, H.⁴ Stricker, A.⁵ Fichtber, W.⁶

2
- 84949001572
- High voltage drain-extended devices for .18m digital CMOS process
- J. Mitros, C.Y. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster, D. Mosher, T. Efland, High Voltage Drain-Extended Devices for .18m Digital CMOS Process, ESSDERC, 2000
- (2000) ESSDERC
- Mitros, J.¹ Tsai, C.Y.² Shichijo, H.³ Kunz, K.⁴ Morton, A.⁵ Goodpaster, D.⁶ Mosher, D.⁷ Efland, T.⁸

3
- 0033281017
- A high voltage output fabricated on a 2v CMOS technology
- L. Clark, A High Voltage Output Fabricated on a 2V CMOS Technology, Symp. on VLSI Circuits, pp61-62, 1999
- (1999) Symp. on VLSI Circuits , pp. 61-62
- Clark, L.¹

4
- 0034543814
- Investigation of different protection strategies devoted to 3.3 v rf applications (2 ghz) in a 0.18 m CMOS process
- C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, Investigation of Different Protection Strategies Devoted to 3.3 V RF Applications (2 GHz) in a 0.18 m CMOS Process, EOS/ESD Symp. Proc., 2000
- (2000) EOS/ESD Symp. Proc
- Richier, C.¹ Salome, P.² Mabboux, G.³ Zaza, I.⁴ Juge, A.⁵ Mortini, P.⁶

5
- 0029517845
- Efficient NPN operation in high voltage NMOSFET for ESD robustness
- . C. Duvvury, D. Briggs, J. Rodriguez, F. Cavajal, A. Young, D. Redwine, and M. Smayling, Efficient NPN Operation in High Voltage NMOSFET for ESD Robustness, IEDM Digest, 1995
- (1995) IEDM Digest
- Duvvury, C.¹ Briggs, D.² Rodriguez, J.³ Cavajal, F.⁴ Young, A.⁵ Redwine, D.⁶ Smayling, M.⁷

6
- 0028737473
- Device integration for ESD robustness of high voltage power MOSFETS
- C. Duvvury, J. Rodriguez, C. Jones, and M. Smayling, Device Integration for ESD Robustness of High Voltage Power MOSFETS, IEDM Digest, 1994
- (1994) IEDM Digest
- Duvvury, C.¹ Rodriguez, J.² Jones, C.³ Smayling, M.⁴

7
- 0029506125
- Advanced CMOS protection device trigger mechanisms during CDM
- C. Duvvury , A. Amerasekera, Advanced CMOS Protection Device Trigger Mechanisms During CDM, EOS/ESD Symposium, pp 162-174, 1995
- (1995) EOS/ESD Symposium , pp. 162-174
- Duvvury, C.¹ Amerasekera, A.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.