A model-based methodology for application specific energy efficient data path design using FPGAs

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2002-January, Issue , 2002, Pages 76-87

  Mohanty, S ^a   Choi, S ^a   Jang, Ju Wook ^b   Prasanna, V K ^a  

^a Univ of Southern California ^*  (United States)

^b Sogang University   (South Korea)

Author keywords

Delay; Design methodology; Design optimization; Energy dissipation; Energy efficiency; Field programmable gate arrays; Kernel; Measurement; Signal processing algorithms; Space exploration

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DESIGN; ENERGY DISSIPATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; MEASUREMENTS; OPTIMIZATION; SIGNAL PROCESSING; SPACE RESEARCH; SYSTEMS ANALYSIS;

DELAY; DESIGN METHODOLOGY; DESIGN OPTIMIZATION; KERNEL; SIGNAL PROCESSING ALGORITHMS; SPACE EXPLORATIONS;

ENERGY EFFICIENCY;

EID: 84924377105     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030706     Document Type: Conference Paper

References (18)

1. A. Agrawal, A. Bakshi, J. Davis, B. Eames, A. Ledeczi, S. Mohanty, V. Mathur, S. Neema, G. Nordstrom, V. Prasanna, C. Raghavendra, M. Singh, "MILAN: A Model Based Integrated Simulation for Design of Embedded Systems," Language Compilers and Tools for Embedded Systems, 2001.
2. K. Bondalapati and V. K. Prasanna, "Loop Pipelining and Optimization for Reconfigurable Architectures," Reconfigurable Architectures Workshop (RAW), May 2000.
3. S. Choi, S. Mohanty, J. Jang, and V. K. Prasanna, "Domain-Specific Modeling for Rapid System-Level Energy Estimation of Reconfigurable Architectures," Intl. Conference on Engineering of Reconfigurable Systems and Algorithms, 2002.
4. A. Dandalis and V. K. Prasanna, "Signal Processing using Reconfigurable System-on-Chip Platforms," International Conference on Engineering of Reconfigurable Systems and Algorithms, June 2001.
5. J. A. B. Fortes, K. S. Fu, and B. Wah, "Systematic Approaches to the Design of Algorithmically Specified Systolic Arrays," International Conference on Acoustics, Signal and Speech Processing, 1985.
6. A. Garcia, W. Burleson, and J.L. Danger, "Power Modeling in FPGAs," 9th International Conference on Field Programmable Logic and Applications, 1999.
7. J. Jang, S. Choi, and V. K. Prasanna, "Energy-Efficient Matrix Multiplication on FPGAs," Manuscript, Dept. of Electrical Engg., University of Southern California, April, 2002.
8. D. Kumar and K. Parhi, "Performance Trade-off of DCT Architectures in Xilinx FPGAs," The 33rd Asilomar Conference on Signals, Systems, and Computers, 1999.
9. V. Kumar, A. Grama, A. Gupta, and G. Karypis, "Introduction to Parallel Computing: Design and Analysis of Algorithms," Benjamin Cummings, November, 1993.
10. S. Lei and K. Yao, "Efficient Systolic Array Implementations of Digital Filtering," IEEE International Symposium on Circuits and Systems, 1989.
11. W. Luk, N. Shirazi, and P.Y.K. Cheung, "Modeling and Optimizing Run-time Reconfigurable Systems," IEEE Symposium on FPGAs for Custom Computing Machines, 1996.
12. Model-based Integrated Simulation, http://milan.usc.edu/.
13. S. Mohanty, V. K. Prasanna, S. Neema, and J. Davis, "Rapid Design Space Exploration of Heterogeneous Embedded Systems using Symbolic Search and Multi-Granular Simulation," Language Compilers and Tools for Embedded Systems, 2002.
14. M. Nemani and F. N. Najm, "High-level Area and Power Estimation for VLSI Circuits," IEEE/ACM International Conference on Computer-Aided Design, 1997.
15. V. K. Prasanna Kumar and Y. Tsai, "On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication," IEEE Transactions on Computers, Vol. 40, No. 6, 1991.
16. A. Raghunathan, N. K. Jha, and S. Dey, "High-level Power Analysis and Optimization," Kluwer Academic Publishers, 1998
17. F. G. Wolff, M. J. Knieser, D. J. Weyer, C. A. Papachristou, "High-level Low Power FPGA Design Methodology," National Aerospace and Electronics Conference, 2000.
18. Xilinx Application Note: Virtex-II/Virtex-II Pro Series and Xilinx ISE 4.1 Design Environment, http://www.xilinx.com.