Improved scheduler for multi-core many-core systems

Computing

Volumn 96, Issue 11, 2014, Pages 1087-1110

  Kumar, Neetesh ^a   Vidyarthi, Deo Prakash ^a  

^a JAWAHARLAL NEHRU UNIVERSITY   (India)

Author keywords

Effective time; Heterogeneous system; Memory latency; Speedup; Thread

Indexed keywords

LEGACY SYSTEMS; SCHEDULING;

EFFECTIVE TIME; HETEROGENEOUS SYSTEMS; MEMORY LATENCIES; SPEEDUP; THREAD;

MEMORY ARCHITECTURE;

EID: 84919463988     PISSN: 0010485X     EISSN: 14365057     Source Type: Journal    
DOI: 10.1007/s00607-014-0420-y     Document Type: Article

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