Recent advances and future trends of ULSI technologies

European Solid-State Device Research Conference

Volumn , Issue , 1996, Pages 45-52

  Iwai, Hiroshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FUTURE TRENDS;

EID: 84908207076     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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2. R H Dennard, F H Gaensslen, H-N, Yu, V L Rideout, E Bassous, and A. R LeBlanc, "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J Solid-State Circuits, SC-9, pp 256-268,1974
3. J Chung, M.-C Jeng, J E Moon, A T. Woo, T Y Chan, P K Ko, and C Hu, "Deep-submicrometer MOS device fabrication using a photoresist-ashing technique," IEEE Electron Device Lett., EDL-9, pp 186-188,1988
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5. H S Momose, M Ono, T Yoshitomi, T Ohguro, S Nakamura, M Saito, and H Iwai, 'Tunneling gate oxide approach to ultrahigh current dnve in small-geometry MOSFETs," IEDM Tech pp 593-596,1994
6. T Yoshitomi, M. Saito, T Ohguro, M Ono, H S Momose, and H Iwai, "Suicided silicon-sidewaU source and drain (S4D) structure for high-performance 75-nm gate length p-MOSFETs," Symp on VLSI Tech, pp 11-12,1995
7. T Ohguro, N Sugryama, K Tmai, K Usuda, M Saito, T Yoshitomi, M Ono, H S Momose, and H Iwai, 'The influence of oxygen at epitaxial Si/Si substrate interface for 0 1 jim epitaxial Si channel n-MOSFETs grown by UHV-CVD," Symp on VLSI Tech, pp 21-22,1995
8. T Ohguro, S Nakamura, M Koike, T Monmoto, A Nishiyama, Y Ushiku, T Yoshitomi, M Ono, M Saito, and H Iwai, "Analysis of resistance behavior in Ti- and Ni-salicided polysicon films", IEEE Trans on Electron Devices, vol.41, December, 1994
9. T Yoshitomi, T Ohguro, M. Saito, M. Ono, E Monfuji, H S Momose, and H Iwai, "High performance 0 15 jim single gate Co salicide CMOS," Symp on VLSI Tech, 1996
10. T Monmoto, H S Momose, Y Ozawa, KL Yamabe, and H Iwai, "Effects of boron penetration and resultant limitations in ultra min pure-oxide and mtnded-oxide gate-films", IEDM Tech., Dig, pp 429-432,1990.
11. H S Momose, S Kitagawa, K. Yamabe, and H Iwai, "Hot earner related phenomena for n- and p-channel MOSFETs with mtnded gate oxide by RTA," IEDM Tech Dig, pp 267-1270, December, 1989
12. M Saito, M Ono, R Fujimoto, C Takahashi, H Tammoto, N Ito, T Ohguro, T Yoshitomi, and H Iwai, "Advantage of small geometry silicon MOSFET's for high-frequency analog application under low power supply voltage of 0 5V," Symp on VLSI Tech.pp 71-71,1995
13. T Ohguro, E Monfuji, M Saito, M Ono, T Yoshitomi, H S Momose, N Ito, and H Iwai, "0 2 Um analog CMOS with low noise figure at 2 GHz operation," Symp very on VLSI Tech, 1996
14. T Ohguro, M Saito, K Endo, M Kakumoto, T Yoshitomi, M Ono, H S Momose, and H Iwai, "A high frequency 0 35 nm gate length power silicon nMOSFET operating with breakdown voltage of 13V," Proc ISPSD, pp 114-118,1995