Impact of random dopant placement on CMOS delay and power dissipation

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 184-187

  Tang, Xinghai ^a   Bowman, Keith A ^a   Eble, John C ^b   De, Vivek K ^c   Meind, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

RANDOM NUMBER GENERATION;

CRITICAL PATH DELAYS; CRITICAL PATHS; DOPANT ATOMS; FUTURE TECHNOLOGIES; PHYSICAL DEVICES; RANDOM DOPANTS; RANDOM PLACEMENT; SUPPLY VOLTAGES;

ELECTRIC LOSSES;

EID: 84907892733     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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