Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth technique

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 243-246

  Hokazono, A ^a   Ohuchi, K ^a   Miyano, K ^a   Mizushima, I ^a   Tsunashima, Y ^a   Toyoshima, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; EPITAXIAL GROWTH; GATES (TRANSISTOR); LEAKAGE CURRENTS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR JUNCTIONS;

SHORT CHANNEL EFFECT (SCE);

CMOS INTEGRATED CIRCUITS;

EID: 0034454168     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)