A fully integrated pillar process for high performance Cu interconnect scheme

Proceedings of the IEEE 1999 International Interconnect Technology Conference, IITC 1999

Volumn , Issue , 1999, Pages 259-261

  Kajita, Akihiro ^a   Higashi, Kazuyuki ^a   Matsunaga, Noriaki ^a   Shibata, Hideki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

METAL CLEANING;

BACK END OF THE LINES; CONVENTIONAL METALS; DUAL DAMASCENE STRUCTURES; ELECTRICAL CHARACTERISTIC; FULLY INTEGRATED; HIGH PERFORMANCE DEVICES; SINGLE DAMASCENE; WIRE RESISTANCE;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84907562876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1999.787138     Document Type: Conference Paper

References (4)

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