A 2-GHz low-power single-chip CMOS receiver for WCDMA applications

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 57-60

  Yee, Dennis ^a   Doan, Chinh ^a   Sobel, David ^a   Limketkai, Brian ^a   Alalusi, Sayf ^a   Brodersen, Robert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CMOS RECEIVERS; DIRECT-CONVERSION ARCHITECTURE; FIRST-ORDER; QUADRATURE SIGNAL; RF COMPONENTS; SECOND ORDERS; VOLTAGE GAIN;

ANALOG TO DIGITAL CONVERSION; HIGH PASS FILTERS; LOW NOISE AMPLIFIERS;

SIGNAL RECEIVERS;

EID: 70949084675     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. C. Teuscher, D. Yee, N. Zhang, and R. Brodersen, "Design of a Wideband Spread Spectrum Radio Using Adaptive Multiuser Detection," IEEE ISCAS, May 1998, pp. 593-599.
2. B. Razavi, "A 2.4-GHz CMOS Receiver for IEEE 802.11 Wireless LAN's," IEEE JSSC, vol. 34, no.10, October 1999, pp. 1382-1385.
3. A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, and K. Halonen, "A 2-GHz Wide-Band Direct Conversion Receiver for WCDMA Applications," IEEE JSSC, vol. 34, no. 12, December 1999, pp. 1893-1903.
4. D. Shaeffer and T. Lee, "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier," IEEE JSSC, vol. 332, no. 5, May 1997, pp. 745-759.
5. L. Lin, L. Tee, and P. Gray, "A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL Architecture," IEEE ISSCC, February 2000, pp. 204-205.
6. H.-K. Yang and M. Snelgrove, "Symbol Timing Recovery Using Oversampling Techniques," IEEE International Conference on Communications, June 1996, pp. 1296-1300.