Proposal of a single-transistor-cell-type ferroelectric memory using an SOI structure and experimental study on the interference problem in the write operation

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 36, Issue 3 SUPPL. B, 1997, Pages 1655-1658

  Ishiwara, Hiroshi ^a   Shimamura, Toshishige ^a   Tokumitsu, Eisuke ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Ferroelectric memory; FET matrix; MFSFET (metal ferroelectric semiconductor field effect transistor); SOI (silicon on insulator); SrBi2Ta2O9

Indexed keywords

EID: 0000053932     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.36.1655     Document Type: Article

References (5)

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4. H. Ishiwara: Jpn. J. Appl. Phys. 32 (1993) 442.
5. D. J. Taylor, P. K. Larsen and R. Cuppens: Appl. Phys. Lett. 64 (1994) 1392.