A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII

Volumn , Issue , 2014, Pages

  Ishibashi, Koichiro ^a   Sugii, Nobuyuki ^b   Usami, Kimiyoshi ^c   Amano, Hideharu ^d   Kobayashi, Kazutoshi ^e   Pham, Cong Kha ^a   Makiyama, Hideki ^b   Yamamoto, Yoshiki ^b   Shinohara, Hirofumi ^b   Iwamatsu, Toshiaki ^b   Yamaguchi, Yasuo ^b   Oda, Hidekazu ^b   Hasegawa, Takumi ^b   Okanishi, Shinobu ^b   Yanagita, Hiroshi ^b   Kamohara, Shiro ^b   Kadoshima, Masaru ^b   Maekawa, Keiichi ^b   Yamashita, Tomohiro ^b   Le, Duc Hung ^a   Yomogita, Takumu ^a   Kudo, Masaru ^c   Kitamori, Kuniaki ^d   Kondo, Shuya ^e   Manzawa, Yuuki ^e   more..

^a UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

^b Low power Electronics Association and Project LEAP   (Japan)

^c SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^d KEIO UNIVERSITY   (Japan)

^e KYOTO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

CMOS; MCU; SOI; SOTB

Indexed keywords

CMOS TECHNOLOGY; LOW POWER PERFORMANCE; MCU; PERPETUUM MOBILE; REVERSE BODY BIAS; SOI; SOTB; THIN BURIED OXIDES;

CMOS INTEGRATED CIRCUITS;

EID: 84904643914     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CoolChips.2014.6842954     Document Type: Conference Paper

References (3)

1. Y. Yamamoto, H. Makiyama, H. Shinohara, T. Iwamatsu et al.,"Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias," VLSI Technology Symposium , pp. T212-213, June 2013.
2. S. Jain, S. Khare, S. Yada, A. V et al., "A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS," ISSCC Dig. Tech. Papers, pp. 66-67, Feb., 2012.
3. G. Chen, M. Fojtik, D. Kim, D. Fick et al., "Millimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells," ISSCC Dig. Tech. Papers, pp. 288-289, Feb., 2010.