SoC power integrity from early estimation to design sign off

DesignCon 2014: Where the Chip Meets the Board

Volumn , Issue , 2014, Pages

  Yang, Melinda ^a   You, Eileen ^a   Gundurao, Anil ^a   Gill, Harpreet ^a  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

Power integrity; Power system modeling; SoC

Indexed keywords

PROGRAMMABLE LOGIC CONTROLLERS;

COMMERCIAL TOOLS; COMPREHENSIVE SYSTEM; DESIGN DECISION-MAKING; DESIGN TRADEOFF; LOW POWER; POWER INTEGRITY; POWER SYSTEM MODEL; SOC;

SYSTEM-ON-CHIP;

EID: 84904117638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. Gupta, S. Baswant, S. Pillai, P. Koduri, V. Nguyen, S. Mukka, "High performance SoCs: Effective Strategies for achieving optimal performance, power & faster design closures", Mar. 2013, SNUG Silicon Valley.
2. L. Smith, S. Sun, P. Boyle, B. Krsnik, "System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing", Sep. 2009, Custom Integrated Circuits Conference, pp 621-628.
3. S.Lin, M. Nagata, K. Shimazaki, K.Satoh, M. Sumita, H. Tsujikawa, A. Yang, "Full-chip vector-less dynamic power integrity analysis and verification against 100uv/100ps resolution", Oct. 2004, Custom Integrated Circuits Conference, pp 509-512.
4. R. Schmitt, X.Huang, L. Yang, C. Yuan, "System-level power integrity analysis and correlation for multi-gigabit designs", Feb. 2004, Design Con 2004.