Strategies to accelerate harmonic minimization in multilevel inverters using a parallel genetic algorithm on graphical processing unit

IEEE Transactions on Power Electronics

Volumn 29, Issue 10, 2014, Pages 5087-5090

  Roberge, Vincent ^a   Tarbouchi, Mohammed ^a   Okou, Francis ^a  

^a ROYAL MILITARY COLLEGE OF CANADA   (Canada)

Author keywords

Genetic algorithm (GA); graphical processing unit (GPU); multilevel inverter; parallel algorithm

Indexed keywords

ALGORITHMS; ELECTRIC INVERTERS; ELECTROMAGNETIC PULSE; GENETIC ALGORITHMS; HARMONIC ANALYSIS; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; REAL TIME CONTROL;

GRAPHICAL PROCESSING UNIT (GPUS); GRAPHICAL PROCESSING UNITS; HIGH-POWER INVERTERS; HIGH-VOLTAGE OPERATION; MULTILEVEL INVERTER; PARALLEL GENETIC ALGORITHMS; PARALLEL IMPLEMENTATIONS; TOTAL HARMONIC DISTORTION (THD);

COMPUTER GRAPHICS EQUIPMENT;

EID: 84902181492     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2014.2311737     Document Type: Article

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