Highly scalable raised source/drain InAs quantum well MOSFETs exhibiting ION = 482 μA/μm at IOFF = 100 nA/μm and V DD = 0.5 V

IEEE Electron Device Letters

Volumn 35, Issue 6, 2014, Pages 621-623

  Lee, Sanghoon ^a   Huang, Cheng Ying ^a   Cohen Elias, Doron ^a   Thibeault, Brian J ^a   Mitchell, William ^a   Chobpattana, Varistha ^a   Stemmer, Susanne ^a   Gossard, Arthur C ^a   Rodwell, Mark J W ^a  

^a University of California   (United States)

Author keywords

III V MOSFETs; InAs channel; S D regrowth; vertical spacer

Indexed keywords

DRAIN CURRENT; INDIUM ARSENIDE; METALLORGANIC CHEMICAL VAPOR DEPOSITION; SEMICONDUCTOR QUANTUM WELLS;

DRAIN-INDUCED BARRIER LOWERING; EPITAXIAL REGROWTH; III-V MOSFETS; INAS; PEAK TRANSCONDUCTANCE; RAISED SOURCE/DRAIN; S/D REGROWTH; VERTICAL SPACER;

MOSFET DEVICES;

EID: 84901494083     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2014.2317146     Document Type: Article

References (14)

1. J. Lin et al., "A new self-aligned quantum-well MOSFET architecture fabricated by a scalable tight-pitch process," in Proc. IEEE IEDM, Dec. 2013, pp. 421-424.
2. d = 0.5 V)," in Proc. IEEE IEDM, Dec. 2013, pp. 417-420.
3. 2 (EOT = 0.8 nm) composite insulator," in Proc. IEEE IEDM, Dec. 2012, pp. 32.2.1-35.2.4.
4. 0.47As channel metal-oxide-semiconductor field-effecttransistors with reduced leakage using a vertical spacer," Appl. Phys. Lett., vol. 103, no. 23, p. 233503, 2013.
5. S. Kim et al., "High performance sub-20-nm-channel-length extremelythin body InAs-on-insulator tri-gate MOSFETs with high short channel effect immunity and Vth tunability," in Proc. IEEE IEDM, Dec. 2013, pp. 429-432.
6. 0.3As quantum well field effect transistors on silicon substrate for low power logic applications," in Proc. IEEE IEDM, Dec. 2009, pp. 319-322.
7. T.-W. Kim et al., "ETB-QW InAs MOSFET with scaled body for improved electrostatics," in Proc. IEEE IEDM, Dec. 2012, pp. 776-779.
8. V. Chobpattana et al., "Nitrogen-passivated dielectric/InGaAs interfaces with sub-nm equivalent oxide thickness and low interface trap densities," Appl. Phys. Lett., vol. 102, p. 022907, Jan. 2013.
9. D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. New York, NY, USA: Wiley, 2006.
10. 2 (EOT < 1 nm) for low-power logic applications," in Proc. IEEE IEDM, Dec. 2013, pp. 429-432.
11. J. J. Gu et al., "20-80 nm channel length InGaAs gate-all-around nanowire MOSFETs with EOT= 1.2 nm and lowest SS = 63 mV/dec," in Proc. IEEE IEDM, Dec. 2012, pp. 636-639.
12. M. Radosavljevic et al., "Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation," in Proc. IEEE IEDM, Dec. 2011, pp. 765-768.
13. 0.47As MOSFET," in Proc. IEEE IEDM, Dec. 2011, pp. 304-307.
14. S. C. Lee, D. L. Huffaker, and S. R. J. Brueck, "Faceting of a quasi-twodimensional GaAs crystal in nanoscale patterned growth," Appl. Phys. Lett., vol. 92, no. 2, p. 023103, 2008.