Spike anneal peak temperature impact on 1T-DRAM retention time

IEEE Electron Device Letters

Volumn 35, Issue 6, 2014, Pages 639-641

  Nissimoff, Albert ^a,b   Martino, Joao Antonio ^a   Aoulaiche, Marc ^b   Veloso, Anabela ^b   Witters, Liesbeth J ^b   Simoen, Eddy ^b   Claeys, Cor ^b,c  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b IMEC   (Belgium)

^c Katholieke Universiteit Leuven   (Belgium)

Author keywords

1T DRAM; Capacitorless DRAM; SOI

Indexed keywords

ELECTRON DEVICES; ELECTRONICS ENGINEERING;

1T DRAMS; CAPACITORLESS DRAMS; DYNAMIC RANDOM ACCESS MEMORY; LOWER TEMPERATURES; PROCESS TEMPERATURE; SILICON-ON-INSULATOR TRANSISTORS; SOI; TEMPERATURE DIFFERENCES;

SILICON WAFERS;

EID: 84901493638     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2014.2319094     Document Type: Article

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