Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function

Neurocomputing

Volumn 140, Issue , 2014, Pages 228-241

  Nambiar, Vishnu P ^a   Khalil Hani, Mohamed ^b   Sahnoun, Riadh ^b   Marsono, M N ^b  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

^b UNIVERSITI TEKNOLOGI MALAYSIA   (Malaysia)

Author keywords

Activation functions; Block based neural networks (BbNNs); Digital design; Hardware neural network; System on chip (SoC)

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHEMICAL ACTIVATION; COMPUTER HARDWARE; COSTS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NEURONS; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE HARDWARE; STRUCTURAL OPTIMIZATION; SYSTEM-ON-CHIP; TIME SERIES ANALYSIS;

ACTIVATION FUNCTIONS; BLOCK-BASED NEURAL NETWORKS; DESIGN CONSIDERATIONS; DIGITAL DESIGNS; HARDWARE IMPLEMENTATIONS; HARDWARE NEURAL NETWORKS; HYPERBOLIC TANGENT; SIMULTANEOUS OPTIMIZATION;

HARDWARE;

ARTICLE; ARTIFICIAL NEURAL NETWORK; BLOCK BASED NEURAL NETWORK; COMPUTER; COST UTILITY ANALYSIS; DUAL PORT ON CHIP; FIELD PROGRAMMABLE GATE ARRAY; NANOCHIP; NERVE CELL; PRIORITY JOURNAL; PROCESS OPTIMIZATION;

EID: 84901488781     PISSN: 09252312     EISSN: 18728286     Source Type: Journal    
DOI: 10.1016/j.neucom.2014.03.018     Document Type: Article

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