A simple characterization method for MOS transistor matching in deep submicron technologies

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2001, Pages 213-218

  Croon, J A ^a   Rosmeulen, M ^a   Decoutere, S ^a   Sansen, W ^a   Maes, H E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; MATHEMATICAL MODELS; MOS DEVICES; THRESHOLD VOLTAGE; TRANSISTORS;

DRAIN CURRENT; MOS TRANSISTOR MATCHING; THRESHOLD VOLTAGE MISMATCH;

INTEGRATED CIRCUIT TESTING;

EID: 0034860974     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits
2. Matching properties of MOS transistors
3. The design of high-performance analog circuits on digital CMOS chips
4. Random error effects in matched MOS capacitors and current sources
5. Characterization and modeling of mismatch in MOS transistors for precision analog design
6. Mismatch characterization of submicron MOS transistors
7. A new five-parameter MOS transistor mismatch model
8. Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation
9. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors