Fast polar decoders: Algorithm and implementation

IEEE Journal on Selected Areas in Communications

Volumn 32, Issue 5, 2014, Pages 946-957

  Sarkis, Gabi ^a   Giard, Pascal ^a,c   Vardy, Alexander ^b   Thibeault, Claude ^c   Gross, Warren J ^a  

^a MCGILL UNIVERSITY   (Canada)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c ÉCOLE DE TECHNOLOGIE SUPÉRIEURE   (Canada)

Author keywords

polar codes; storage systems; successive cancellation decoding

Indexed keywords

DECODING;

ALGORITHM AND IMPLEMENTATION; DECODING ALGORITHM; EXPLICIT CONSTRUCTIONS; FPGA IMPLEMENTATIONS; MEMORYLESS CHANNELS; POLAR CODES; STORAGE SYSTEMS; SUCCESSIVE-CANCELLATION DECODING;

ALGORITHMS;

EID: 84899828799     PISSN: 07338716     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSAC.2014.140514     Document Type: Article

References (14)

1. E. Arikan, "Channel polarization: A method for constructing capacityachieving codes for symmetric binary-input memoryless channels," IEEE Trans. Inf. Theory, vol. 55, no. 7, pp. 3051-3073, 2009.
2. A. Eslami and H. Pishro-Nik, "On bit error rate performance of polar codes in finite regime," in Proc. 48th Annual Allerton Conf. Communication, Control, and Computing (Allerton), 2010, pp. 188-194.
3. C. Leroux, A. Raymond, G. Sarkis, and W. Gross, "A semi-parallel successive-cancellation decoder for polar codes," IEEE Trans. Signal Process., vol. 61, no. 2, pp. 289-299, 2013.
4. I. Tal and A. Vardy, "List decoding of polar codes," CoRR, vol. abs/1206.0050, 2012. [Online]. Available: http://arxiv.org/abs/1206.0050v1
5. P. Chicoine, M. Hassner, M. Noblitt, G. Silvus, B. Weber, and E. Grochowski, "Hard disk drive long data sector white paper," Technical report, The International Disk Drive Equipment and Materials Association (IDEMA), Tech. Rep., 2007.
6. A. Alamdar-Yazdi and F. R. Kschischang, "A simplified successivecancellation decoder for polar codes," IEEE Commun. Lett., vol. 15, no. 12, pp. 1378-1380, 2011.
7. G. Sarkis and W. J. Gross, "Increasing the throughput of polar decoders," IEEE Commun. Lett., vol. 17, no. 4, pp. 725-728, 2013.
8. A. Pamuk and E. Arikan, "A two phase successive cancellation decoder architecture for polar codes," in Proc. IEEE International Symposium on Information Theory ISIT 2013, Jul. 2013, pp. 1-5.
9. I. Tal and A. Vardy, "How to construct polar codes," CoRR, vol. abs/1105.6164, 2011. [Online]. Available: http://arxiv.org/abs/1105.6164
10. E. Arikan, "Systematic polar coding," IEEE Commun. Lett., vol. 15, no. 8, pp. 860-862, 2011.
11. A. Mishra, A. Raymond, L. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, and W. Gross, "A successive cancellation decoder asic for a 1024-bit polar code in 180nm cmos," in Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian, 2012, pp. 205-208.
12. J. Snyders and Y. Be'ery, "Maximum likelihood soft decoding of binary block codes and decoders for the Golay codes," IEEE Trans. Inf. Theory, vol. 35, no. 5, pp. 963-975, 1989. (Pubitemid 20630578)
13. A. Alamdar-Yazdi and F. R. Kschischang, "Locally-reduced polar codes," personal communication, 2012.
14. V. Torres, A. Perez-Pascual, T. Sansaloni, and J. Valls, "Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA," in Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on, 2012, pp. 408-411.