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Volumn 61, Issue 2, 2013, Pages 289-299

A Semi-parallel successive-cancellation decoder for polar codes

Author keywords

Codes; decoding; FPGA; polar codes; successive cancellation; VLSI

Indexed keywords

CODES; CODING THEORY; MEMORY COMPLEXITY; POLAR CODES; PROCESSING COMPLEXITY; PROCESSING RESOURCES; RECURSIVE STRUCTURE; SEMI-PARALLEL ARCHITECTURE; SUCCESSIVE CANCELLATION; SUCCESSIVE-CANCELLATION DECODING; VLSI;

EID: 84871768217     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2012.2223693     Document Type: Article
Times cited : (320)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.