Test-driving Intel Xeon Phi

ICPE 2014 - Proceedings of the 5th ACM/SPEC International Conference on Performance Engineering

Volumn , Issue , 2014, Pages 137-148

  Fang, Jianbin ^a   Xu, Chuanfu ^b   Sips, Henk ^a   Che, Yonggang ^b   Zhang, Lilun ^b   Varbanescu, Ana Lucia ^c  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

^c UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

Experience with Xeon Phi; Microbenchmarking; Optimization; Performance analysis

Indexed keywords

COMPUTER ARCHITECTURE; MEDICAL IMAGING; OPTIMIZATION; PROGRAM PROCESSORS;

APPLICATION LEVEL; EXPERIENCE WITH XEON PHI; FUNCTIONAL CODES; IMAGING APPLICATIONS; MASSIVE PARALLELISM; MICRO-BENCHMARKING; PARALLELIZATIONS; PERFORMANCE ANALYSIS;

BENCHMARKING;

EID: 84899675168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2568088.2576799     Document Type: Conference Paper

References (29)

1. R. D. e. a. Blumofe. Cilk: an efficient multithreaded runtime system. SIGPLAN Not., 30(8):207-216, Aug. 1995.
2. O. A. R. Board. OpenMP application program interface (version 4.0). Technical report, July 2013.
3. M. Boyer et al. Accelerating leukocyte tracking using CUDA: A case study in leveraging manycore coprocessors. In IPDPS'09, May 2009.
4. K. Datta et al. Optimization and performance modeling of stencil computations on modern microprocessors. SIAM Rev., 51(1):129-159, Feb. 2009.
5. David. Programming with POSIX Threads. May 1997.
6. J. Fang et al. Benchmarking intel xeon phi to guide kernel design. Technical Report PDS-2013-005, Delft University of Technology, Apr. 2013.
7. A. Fog. Lists of instruction latencies, throughputs and micro-operation reakdowns. Technical report, Copenhagen University, Feb. 2012.
8. S. R. Garea and T. Hoefler. Modeling Communication in Cache-Coherent SMP Systems - A Case-Study with Xeon Phi. 2013. HPDC'13.
9. T. Granlund. Instruction latencies and throughput for AMD and intel x86 processors. Technical report, KTH, Feb. 2012.
10. J. L. Hennessy and D. A. Patterson. Computer Architecture, Fifth Edition: A Quantitative Approach. Morgan Kaufmann, 5 edition, Sept. 2011.
11. Intel. Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual, Sept. 2012.
12. Intel. Intel Xeon Phi Coprocessor System Software Development Guide, Nov. 2012.
13. Intel. An Overview of Programming for Intel Xeon Processors and Intel Xeon Phi Coprocessors, Oct. 2012.
14. Intel. Streaming Store Instructions in the Intel Xeon Phi coprocessor, 2012.
15. Intel. Intel Xeon Phi Coprocessor. http://software.intel.com/mic- developer, April 2013.
16. John D. McCalpin. STREAM: Sustainable Memory Bandwidth With High Performance Computers, April 2013.
17. V. W. Lee et al. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. SIGARCH Comput. Archit. News, 38(3), June 2010.
18. L. McVoy et al. lmbench: portable tools for performance analysis. In USENIX ATEC'96, 1996.
19. D. Molka et al. Memory performance and cache coherency effects on an intel nehalem multiprocessor system. In PACT'09., Sept. 2009.
20. L. Peng et al. Memory hierarchy performance measurement of commercial dual-core desktop processors. Journal of Systems Architecture, 54(8):816-828, Aug. 2008.
21. N. Ray et al. Motion gradient vector flow: an external force for tracking rolling leukocytes with shape and size constrained active contours. Medical Imaging, IEEE Transactions on, Dec. 2004.
22. A. Sclocco et al. Radio astronomy beam forming on Many-Core architectures. In IPDPS, 2012.
23. A. J. Smith et al. Measuring cache and TLB performance and their effect on benchmark runtimes. IEEE Trans. Comput., (10), Oct. 1995.
24. J. E. Stone et al. OpenCL: A parallel programming standard for heterogeneous computing systems. Computing in science & engineering, 12(3):66-72, May 2010.
25. Technical University of Dresden. BenchIT: Performance Measurement for Scientific Applications, August 2013.
26. P. Thoman et al. Automatic OpenCL device characterization: Guiding optimized kernel design. In Euro-Par'11. 2011.
27. A. L. Varbanescu, A. S. van Amesfoort, T. Cornwell, G. van Diepen, R. van Nieuwpoort, B. G. Elmegreen, and H. J. Sips. Building high-resolution sky images using the Cell/B.e. Scientific Programming, 17(1-2):113-134, 2009.
28. V. Volkov and J. W. Demmel. Benchmarking GPUs to tune dense linear algebra. In High Performance Computing, Networking, Storage and Analysis, 2008. SC 2008. International Conference for, pages 1-11. IEEE, Nov. 2008.
29. H. Wong, M.-M. Papadopoulou, M. Sadooghi-Alvandi, and A. Moshovos. Demystifying GPU microarchitecture through microbenchmarking. In 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS), pages 235-246. IEEE, Mar. 2010.