-
2
-
-
84898644158
-
-
Inquiry into Counterfeit Electronic Parts in the Department of Defense Supply Chain, United States Senate
-
Inquiry into Counterfeit Electronic Parts in the Department of Defense Supply Chain, Committee on Armed Services, United States Senate (2012).
-
(2012)
Committee On Armed Services
-
-
-
3
-
-
84898645976
-
-
Digilent, Inc.: Nexys4TM FPGA Board Reference Manual, 2013
-
Digilent, Inc.: Nexys4TM FPGA Board Reference Manual (2013).
-
-
-
-
4
-
-
84872574199
-
A stable chip-ID generating physical uncloneable function using random address errors in SRAM
-
SOCC 2012
-
Fujiwara, H., Yabuuchi, M., Tsukamoto, Y., Nakano, H., Owada, T., Kawai, H. and Nii, K.: A stable chip-ID generating physical uncloneable function using random address errors in SRAM, SOCC 2012, pp.143-147, IEEE (2012).
-
(2012)
IEEE
, pp. 143-147
-
-
Fujiwara, H.1
Yabuuchi, M.2
Tsukamoto, Y.3
Nakano, H.4
Owada, T.5
Kawai, H.6
Nii, K.7
-
5
-
-
0038341105
-
Silicon Physical Random Functions
-
CCS 2002
-
Gassend, B., Clarke, D., van Dijk, M. and Devadas, S.: Silicon Physical Random Functions, CCS 2002, pp.148-160, ACM (2002).
-
(2002)
ACM
, pp. 148-160
-
-
Gassend, B.1
Clarke, D.2
van Dijk, M.3
Devadas, S.4
-
7
-
-
38049015807
-
FPGA Intrinsic PUFs and Their Use for IP Protection
-
Guajardo, J., Kumar, S.S., Schrijen, G.-J. and Tuyls, P.: FPGA Intrinsic PUFs and Their Use for IP Protection, CHES'07, pp.63-80 (2007).
-
(2007)
CHES'07
, pp. 63-80
-
-
Guajardo, J.1
Kumar, S.S.2
Schrijen, G.-J.3
Tuyls, P.4
-
8
-
-
84856829954
-
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function
-
(Anonymized for review)
-
(Anonymized for review): Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function, ReConFig2011, pp.223-228 (2011).
-
(2011)
ReConFig2011
, pp. 223-228
-
-
-
9
-
-
84898661331
-
Performance Evaluation of Physical Unclonable Functions on 45-nm Process FPGAs
-
(Anonymized for review), 2012, (in Japanese)
-
(Anonymized for review): Performance Evaluation of Physical Unclonable Functions on 45-nm Process FPGAs, DICOMO 2012, pp.1928-1933 (2012). (in Japanese).
-
(2012)
DICOMO
, pp. 1928-1933
-
-
-
10
-
-
84912102052
-
Performance Evaluation of Physical Unclonable Functions on Kintex-7 FPGA, IEICE Technical Report
-
(Anonymized for review), (in Japanese)
-
(Anonymized for review): Performance Evaluation of Physical Unclonable Functions on Kintex-7 FPGA, IEICE Technical Report, RECONF2013-17, pp.91-96 (2013). (in Japanese).
-
(2013)
RECONF2013-17
, pp. 91-96
-
-
-
11
-
-
79951741378
-
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs, Proc
-
(Anonymized for review)
-
(Anonymized for review): Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs, Proc. ReConFig2010, pp.298-303 (2010).
-
(2010)
ReConFig2010
, pp. 298-303
-
-
-
12
-
-
84898645970
-
-
Information Technology - Trusted Platform Module - Part 1
-
Information Technology - Trusted Platform Module - Part 1: Overview, ISO/IEC 11889-1:2009 (2009).
-
(2009)
Overview, ISO/IEC
, vol.2009
, pp. 11881-11889
-
-
-
13
-
-
84898608840
-
-
Top 5 Most Counterfeited Parts Represent a $169 Billion Potential Challenge for Global Semiconductor Market, iSuppli (2012), available from
-
Top 5 Most Counterfeited Parts Represent a $169 Billion Potential Challenge for Global Semiconductor Market, iSuppli (2012), available from _http://www.isuppli.com/_.
-
-
-
-
14
-
-
84898625426
-
Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing
-
2012
-
Katashita, T., Hori, Y., Sakane, H. and Satoh, A.: Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing, NIAT 2012 (2012).
-
(2012)
NIAT
-
-
Katashita, T.1
Hori, Y.2
Sakane, H.3
Satoh, A.4
-
15
-
-
84939573910
-
Differential power analysis
-
Kocher, P., Jaffe, J. and Jun, B.: Differential power analysis, CRYPTO'99, pp.388-397 (1999).
-
(1999)
CRYPTO'99
, pp. 388-397
-
-
Kocher, P.1
Jaffe, J.2
Jun, B.3
-
16
-
-
84943632039
-
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
-
Kocher, P.C.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, CRYPTO'96, pp.104-113 (1996).
-
(1996)
CRYPTO'96
, pp. 104-113
-
-
Kocher, P.C.1
-
17
-
-
84898645971
-
Security of Pattern Matching Key Generation using Part of PUF Output
-
Komano, Y., Ohta, K., Sakiyama, K. and Mitsugu, I.: Security of Pattern Matching Key Generation using Part of PUF Output, SCIS 2013 (2013).
-
(2013)
SCIS
, pp. 2013
-
-
Komano, Y.1
Ohta, K.2
Sakiyama, K.3
Mitsugu, I.4
-
18
-
-
51849144293
-
The Butterfly PUF
-
Kumar, S.S., Guajardo, J., Maesyz, R., Schrijen, G.-J. and Tuyls, P.: The Butterfly PUF, HOST'08, pp.67-70 (2008).
-
(2008)
HOST'08
, pp. 67-70
-
-
Kumar, S.S.1
Guajardo, J.2
Maesyz, R.3
Schrijen, G.-J.4
Tuyls, P.5
-
20
-
-
85016215043
-
-
, Sadeghi, A.-R. and Naccache, D. (Eds.), chapter 1, Springer-Verlag
-
Maes, R. and Verbauwhede, I.: Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions, Towards Hardware-Intrinsic Security, Sadeghi, A.-R. and Naccache, D. (Eds.), chapter 1, pp.3-37, Springer-Verlag (2010).
-
(2010)
Physically Unclonable Functions: A Study On the State of the Art and Future Research Directions, Towards Hardware-Intrinsic Security
, pp. 3-37
-
-
Maes, R.1
Verbauwhede, I.2
-
22
-
-
78649989155
-
Modeling Attacks on Physical Unclonable Functions
-
CCS 2010
-
Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S. and Schmidhuber, J.: Modeling Attacks on Physical Unclonable Functions, CCS 2010, pp.237-249, ACM (2010).
-
(2010)
ACM
, pp. 237-249
-
-
Rührmair, U.1
Sehnke, F.2
Sölter, J.3
Dror, G.4
Devadas, S.5
Schmidhuber, J.6
-
23
-
-
77953492364
-
Secure implementation of cryptographic modules-Development of a standard evaluation environment for side channel attacks
-
Satoh, A., Katashita, T. and Sakane, H.: Secure implementation of cryptographic modules-Development of a standard evaluation environment for side channel attacks, Synthesiology, Vol.3, No.1, pp.56-65 (2010).
-
(2010)
Synthesiology
, vol.3
, Issue.1
, pp. 56-65
-
-
Satoh, A.1
Katashita, T.2
Sakane, H.3
-
24
-
-
34547307341
-
Physical Physical Unclonable Functions for Device Authentication and Secret Key Generation
-
Suh, G.E. and Devadas, S.: Physical Physical Unclonable Functions for Device Authentication and Secret Key Generation, DAC'07, pp.9-14 (2007).
-
(2007)
DAC'07
, pp. 9-14
-
-
Suh, G.E.1
Devadas, S.2
-
25
-
-
78049343605
-
The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes
-
Suzuki, D. and Shimizu, K.: The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes, Proc. CHES2010, pp.366-382 (2010).
-
(2010)
Proc. CHES2010
, pp. 366-382
-
-
Suzuki, D.1
Shimizu, K.2
-
26
-
-
84898645972
-
-
Xilinx, Inc, Virtex-5 Family Overview
-
Xilinx, Inc.: Virtex-5 Family Overview (2009).
-
(2009)
-
-
-
27
-
-
84898645973
-
-
Xilinx, Inc, Spartan-6 Family Overview
-
Xilinx, Inc.: Spartan-6 Family Overview (2011).
-
(2011)
-
-
-
28
-
-
84898619880
-
-
Xilinx, Inc.: 7 Series FPGAs Overview, (DS180 v1.13)
-
Xilinx, Inc.: 7 Series FPGAs Overview, Advanced Product Specification (DS180 v1.13) (2012).
-
(2012)
Advanced Product Specification
-
-
|