A stable chip-ID generating physical uncloneable function using random address errors in SRAM

International System on Chip Conference

Volumn , Issue , 2012, Pages 143-147

  Fujiwara, Hidehiro ^a   Yabuuchi, Makoto ^a   Tsukamoto, Yasumasa ^a   Nakano, Hirofumi ^a   Owada, Toru ^a   Kawai, Hiroyuki ^a   Nii, Koji ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

OPERATING CONDITION; PHYSICAL UNCLONEABLE FUNCTIONS; RANDOM FAILURES; SCREENING TESTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; HAMMING DISTANCE; RANDOM ERRORS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 84872574199     PISSN: 21641676     EISSN: 21641706     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2012.6398399     Document Type: Conference Paper

References (5)

1. K. Lofstrom, W.R. Daasch, and D. Taylor, "IC Identification Circuit using Device Mismatch" ISSCC, pp. 372-373, February 2000. (Pubitemid 32864183)
2. J. Guajardo, S.S. Kumar, G.-J. Schrijen, and P. Tuyls, "FPGA Intrinsic PUFs and Their Use for IP Protection" CHES, pp. 63-80, September 2007.
3. S. Okumura, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto, "A 128-bit Chip Identification Generating Scheme Exploiting SRAM bitcells with Failure Rate of 4.45 x 10-19" ESSCIRC, pp. 527-530, September 2011.
4. S. Chellappa, A. Dey, L.T. Clark, "Improved Circuits for Microchip Identification using SRAM Mismatch" CICC, pp. 1-4, September 2011.
5. M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, G. Okazaki, K. Satomi, H. Akamatsu, H. Shinohara, "A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations" ISSCC, pp.326-327, February 2007.