RIFFA 2.0: A reusable integration framework for FPGA accelerators

2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings

Volumn , Issue , 2013, Pages

  Jacobsen, Matthew ^a   Kastner, Ryan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; BANDWIDTH; DATA TRANSFER; HARDWARE; OPEN SYSTEMS; PROGRAM PROCESSORS; SOFTWARE TESTING; WINDOWS OPERATING SYSTEM;

COMMUNICATION AND SYNCHRONIZATIONS; FPGA ACCELERATORS; HARDWARE AND SOFTWARE; INTEGRATION FRAMEWORKS; LINK CONFIGURATION; OPEN SOURCES; SYSTEM BUS; XILINX FPGAS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84898653089     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2013.6645504     Document Type: Conference Paper

References (11)

1. R. Kalarot and J. Morris, "Comparison of fpga and gpu implementations of real-time stereo vision," in Computer Vision and Pattern Recognition Workshops (CVPRW), 2010 IEEE Computer Society Conference on, June, pp. 9-15.
2. R. Spurzem, P. Berczik, G. Marcus, A. Kugel, G. Lienhart, I. Berentzen, R. Männer, R. Klessen, and R. Banerjee, "Accelerating astrophysical particle simulations with programmable hardware (fpga and gpu)," Computer Science- Research and Development, vol. 23, no. 3, 2009.
3. S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach, "Accelerating compute-intensive applications with GPUs and FPGAs," in SASP. IEEE, 2008, pp. 101-107.
4. K. H. Tsoi and W. Luk, "Axel: a heterogeneous cluster with fpgas and gpus," in Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2010, pp. 115-124.
5. M. Jacobsen, Y. Freund, and R. Kastner, "Riffa: A reusable integration framework for fpga accelerators," in Field- Programmable Custom Computing Machines (FCCM), 2012. IEEE, 2012, pp. 216-219.
6. J. M. III, "Open component portability infrastructure (opencpi)," 2009.
7. K. Eguro, "SIRC: An extensible reconfigurable computing communication API," in FCCM, R. Sass and R. Tessier, Eds. IEEE Computer Society, 2010, pp. 135-138.
8. W. Peck, E. K. Anderson, J. Agron, J. Stevens, F. Baijot, and D. L. Andrews, "Hthreads: A computational model for reconfigurable devices," in FPL. IEEE, 2006, pp. 1-4.
9. J. H. Kelm and S. S. Lumetta, "Hybridos: runtime support for reconfigurable accelerators," in FPGA. New York, NY, USA: ACM, 2008, pp. 212-221.
10. R. Brodersen, A. Tkachenko, and H. Kwok-Hay So, "A unified hardware/software runtime environment for fpga-based reconfigurable computers using borph," in CODES+ISSS '06, 2006.
11. A. Goldhammer and J. Ayer Jr, "Understanding performance of pci express systems," White Paper: Xilinx Virtex-4 and Virtex-5 FPGAs, 2008.