28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 38-39

  Kimura, Hiroshi ^a   Aziz, Pervez ^a   Jing, Tai ^a   Sinha, Ashutosh ^a   Narayan, Ram ^a   Gao, Hairong ^a   Jing, Ping ^a   Hom, Gary ^a   Liang, Anshi ^a   Zhang, Eric ^a   Kadkol, Aniket ^a   Kothari, Ruchi ^a   Chan, Gordon ^a   Sun, Yehui ^a   Ge, Benjamin ^a   Zeng, Jason ^a   Ling, Kathy ^a   Wang, Michael ^a   Malipatil, Amaresh ^a   Kotagiri, Shiva ^a   Li, Lijun ^a   Abel, Chris ^a   Zhong, Freeman ^a   more..

^a LSI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENTIAL AMPLIFIERS; ELECTRIC INDUCTORS;

ANALOG FRONT-END; EQUALIZATION TECHNIQUES; HIGH-SPEED OPERATION; LOW-POWER CONSUMPTION; ON-CHIP PASSIVES; OPERATING POINTS; TIMING CLOSURES; TRANSIMPEDANCE AMPLIFIERS;

TIMING JITTER;

EID: 84898078721     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757327     Document Type: Conference Paper

References (3)

1. J. Bulzacchelli, et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology," ISSCC Dig. Tech. Papers, pp. 324-325, Feb., 2012.
2. S. Parikh, et al., "A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS," ISSCC Dig. Tech. Papers, pp. 28-29, Feb., 2013.
3. F. Zhong, et at., "A 1.0625-to-14.025Gb/s multimedia transceiver with fullrate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS," ISSCC Dig. Tech. Papers, pp. 348-349, Feb., 2011.