Chip-scale packaging for bioelectronic implants

International IEEE/EMBS Conference on Neural Engineering, NER

Volumn , Issue , 2013, Pages 931-936

  Weiland, James D ^a   Kimock, Fred M ^b   Yehoda, Joseph E ^c   Gill, Emma ^d   McLntosh, Ben P ^e   Nasiatka, Patrick J ^e   Tanguay, Armand R ^e  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b Four Circle Incorporated   (United States)

^c Morgan Advanced Materials Diamonex   (United States)

^d Morgan Advanced Materials Alberox   (United States)

^e University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER PROPERTIES; CHIP-SCALE PACKAGING; EARLY WARNING SYSTEM; HERMETIC PACKAGING; INTEGRATED SENSORS; PACKAGING TECHNOLOGIES; SYSTEM REQUIREMENTS; THREE-DIMENSIONAL STRUCTURE;

ENGINEERING; INDUSTRIAL ENGINEERING;

MULTILAYER FILMS;

EID: 84897688812     PISSN: 19483546     EISSN: 19483554     Source Type: Conference Proceeding    
DOI: 10.1109/NER.2013.6696088     Document Type: Conference Paper

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