IDDT test methodologies for very deep sub-micron CMOS circuits

Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002

Volumn , Issue , 2002, Pages 403-407

  Chehab, Ali ^a   Makki, Rafic ^b   Spica, Michael ^c   Wu, David ^c  

^a Multilink Technology Corporation   (United States)

^b UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

DEFECT SENSITIVITY; DETECTION OF DEFECTS; DOUBLE THRESHOLD; PRODUCTION ENVIRONMENTS; RESISTIVE BRIDGE; TEST METHODOLOGY; TRANSISTOR LEVEL; VERY DEEP SUB MICRONS;

DEFECTS;

EID: 84897519623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2002.994659     Document Type: Conference Paper

References (13)

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