Verifying a self-timed divider

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 146-158

  Ono Tesfaye, Tarik ^a   Kern, Christoph ^a   Greenstreet, Mark R ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; GRAPHIC METHODS;

GRAPH-BASED; HIGH-LEVEL MODELS; MODEL CHECKER; PROOF CHECKERS; SPEED INDEPENDENT; TIMING PROPERTIES; TIMING VERIFICATION; TRANSISTOR LEVEL;

MODEL CHECKING;

EID: 84896827017     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666501     Document Type: Conference Paper

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