Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Volumn , Issue , 2013, Pages

  Tshibangu, Nyunyi M ^a   Franzon, Paul D ^a   Rotenberg, Eric ^a   Davis, William R ^a  

^a North Carolina State University   (United States)

Author keywords

cache; memory; VLSI

Indexed keywords

EID: 84893945367     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2013.6702397     Document Type: Conference Paper

References (7)

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6. CACTI 6.5, http://www.hpl.hp.com/research/cacti/
7. W.R. Davis, J. Wilson, S.Mick, J.Xu, H. Hua, C.Mineo, A. Sule, M.Steer, P. franzon, "Demystifying 3DICs: the pros and cons of going vertical", IEEE design & test of computers, pp. 498-5107, Dec. 2005.