메뉴 건너뛰기




Volumn , Issue , 2003, Pages 576-581

From C programs to the configure-execute model

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL DESCRIPTIONS; COMPUTATIONAL STRUCTURE; MAPPING TECHNIQUES; PERFORMANCE GAIN; PROCESSING PLATFORM; RECONFIGURATION OVERHEAD; SINGLE CONFIGURATION; TEMPORAL PARTITIONING;

EID: 84893733998     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253670     Document Type: Conference Paper
Times cited : (23)

References (15)
  • 2
    • 0005513932 scopus 로고    scopus 로고
    • PACT XPP Technologies AG Munich Germany Release 2.0 June
    • PACT XPP Technologies AG, Munich, Germany, ?The XPP White Paper,? Release 2.0, June 2001. http://www.pactcorp.com
    • (2001) The Xpp White Paper
  • 3
    • 0026925908 scopus 로고
    • The function processor: A data-driven processor array for irregular computations
    • J. Vasell, and J. Vasell. ?The Function Processor: A Data-Driven Processor Array for Irregular Computations,? in Future Generation Computer Systems, 8(4), 1992, pp. 321-335
    • (1992) Future Generation Computer Systems , vol.8 , Issue.4 , pp. 321-335
    • Vasell, J.1    Vasell, J.2
  • 5
    • 84966670525 scopus 로고    scopus 로고
    • Architecture design of reconfigurable pipelined datapaths
    • Atlanta, GA, USA March
    • D. C. Cronquist, et al., ?Architecture Design of Reconfigurable Pipelined Datapaths,? In 20th Anniversary Conf. on Advanced Research in VLSI, Atlanta, GA, USA, March 1999, pp. 23-40
    • (1999) 20th Anniversary Conf. on Advanced Research in VLSI , pp. 23-40
    • Cronquist, D.C.1
  • 7
    • 0343051708 scopus 로고    scopus 로고
    • The stanford suif compiler group
    • SUIF Compiler system, ?The Stanford SUIF Compiler Group,? http://suif.stanford.edu
    • SUIF Compiler System
  • 9
    • 0002230692 scopus 로고
    • Compiling occam into fpgas
    • Will Moore and Wayne Luk, eds Abingdon EE&CS Books, Abingdon, England, UK
    • I. Page, andW. Luk, ?Compiling occam into FPGAs,? In FPGAs, Will Moore and Wayne Luk, eds., Abingdon EE&CS Books, Abingdon, England, UK, 1991, pp. 271-283
    • (1991) FPGAs , pp. 271-283
    • Page, I.1    Luk, W.2
  • 10
    • 84947928895 scopus 로고
    • Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic array
    • LNCS, Springer-Verlag
    • M. Gokhale, and A. Marks, ?Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Array,? in Proc. 5th Int?l Workshop on Field Programmable Logic and Applications (FPL?95), LNCS, Springer-Verlag, 1995, pp. 399-408
    • (1995) Proc. 5th Int?l Workshop on Field Programmable Logic and Applications (FPL?95 , pp. 399-408
    • Gokhale, M.1    Marks, A.2
  • 12
    • 0034174187 scopus 로고    scopus 로고
    • Piperench: A reconfigurable architecture and compiler
    • April
    • S. C. Goldstein, et al., ?PipeRench: A Reconfigurable Architecture and Compiler,? in IEEE Computer, Vol. 33, No. 4, April 2000
    • (2000) IEEE Computer , vol.33 , Issue.4
    • Goldstein, S.C.1
  • 13
    • 84947439562 scopus 로고    scopus 로고
    • An integrated partioning and synthesis system for dynamically reconfigurable multi-fpga architectures
    • Orlando, Florida, USA March 30
    • I. Ouaiss, et al., ?An Integrated Partioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures,? in Proc. 5th Reconfigurable Architectures Workshop (RAW?98), Orlando, Florida, USA, March 30, 1998, pp. 31-36
    • (1998) Proc. 5th Reconfigurable Architectures Workshop (RAW?98 , pp. 31-36
    • Ouaiss, I.1
  • 14
    • 0142130823 scopus 로고    scopus 로고
    • An integrated temporal partitioning and partial reconfiguration technique for design latency improvement
    • Paris, France March 27-30
    • S. Ganesan, and R. Vemuri, ?An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement,? in Proc. Design, Automation & Test in Europe (DATE?00), Paris, France, March 27-30, 2000, pp. 320-325
    • (2000) Proc. Design, Automation & Test in Europe (DATE?00 , pp. 320-325
    • Ganesan, S.1    Vemuri, R.2
  • 15
    • 0035706050 scopus 로고    scopus 로고
    • A framework for reconfigurable computing: Task scheduling and context management
    • Dec
    • R. Maestre, et al., ?A Framework for Reconfigurable Computing: Task Scheduling and Context Management,? in IEEE Transactions on VLSI Systems, Vol. 9, No. 6, Dec. 2001, pp. 858-873
    • (2001) IEEE Transactions on VLSI Systems , vol.9 , Issue.6 , pp. 858-873
    • Maestre, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.