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Volumn 1998-December, Issue , 1998, Pages 317-322

Power and speed-efficient code transformation of multimedia algorithms for RISC processors

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COSINE TRANSFORMS; DATA TRANSFER; DECODING; HARDWARE; IMAGE CODING; MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 84893705204     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MMSP.1998.738953     Document Type: Conference Paper
Times cited : (3)

References (28)
  • 1
    • 0027545019 scopus 로고
    • Managing locality sets: The model and fixed-size buffers
    • Feb
    • A. Choi et al. Managing locality sets: The model and fixed-size buffers. IEEE rfians. on Computers, 42(2):190-204, Feb. 1993.
    • (1993) IEEE Rfians. on Computers , vol.42 , Issue.2 , pp. 190-204
    • Choi, A.1
  • 2
    • 0026368368 scopus 로고
    • Performance analysis through memory of a proposed parailel architecture for the efficient use of' memory in image processing applications
    • Boston MA Oct
    • A. Faruque et.al. Performance analysis through memory of a proposed parailel architecture for the efficient use of' memory in image processing applications. In Proc. SPIE '91, Visual communications and image processing, pages 865-877, Boston MA, Oct. 1991.
    • (1991) Proc. SPIE '91 Visual Communications and Image Processing , pp. 865-877
    • Faruque, A.1
  • 4
    • 84889230950 scopus 로고
    • Digital Video Coding at Telenoi. R & D Feb
    • Digital Video Coding at Telenoi. R & D. Telenor's h.263 software, version 1.3, Feb. 1995. http://www.nta.no/brukere/DVC/h263-software/.
    • (1995) Telenor's h.263 Software, Version 1.3
  • 5
    • 0031674736 scopus 로고    scopus 로고
    • System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs
    • Jan
    • F. Catthoor et al. System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs. Kluwer Journal of VLSI Signal Processing, 18(1):39-50, Jan. 1998.
    • (1998) Kluwer Journal of VLSI Signal Processing , vol.18 , Issue.1 , pp. 39-50
    • Catthoor, F.1
  • 6
    • 0030403093 scopus 로고    scopus 로고
    • Characterizing the memory behavior of compiler-parallelized applications
    • Dec
    • E.Torrie et al. Characterizing the memory behavior of compiler-parallelized applications. IEEE Trans. on Parailel and Distributed Systems, 7(12):1224-1236, Dec. 1996.
    • (1996) IEEE Trans. on Parailel and Distributed Systems , vol.7 , Issue.12 , pp. 1224-1236
    • Torrie, E.1
  • 7
    • 85050113837 scopus 로고    scopus 로고
    • Low power system design
    • B. Brodersen and A. Chandrakasa, editors, Chapter in IEEE Press
    • F. Catthoor et al. Low power System design. In B.Brodersen and A.Chandrakasa, editors, Chapter in "Low power CMOS Design". IEEE Press, 1997.
    • (1997) Low Power CMOS Design
    • Catthoor, F.1
  • 8
    • 0028753469 scopus 로고
    • Analysis of multiprocessor memory reference behavior
    • New York, Oct
    • J. D. Gee et al. Analysis of multiprocessor memory reference behavior. In ICCD, pages 53-59, New York, Oct. 1994.
    • (1994) ICCD , pp. 53-59
    • Gee, J.D.1
  • 10
    • 85050077604 scopus 로고    scopus 로고
    • Program transformation strategies for memory size and power reduction of pseudo-regular multimedia subsystems mapped on multi-processor architectures
    • accepted for publication, Oct. 1998
    • E. De Greef et al. Program transformation strategies for memory size and power reduction of pseudo-regular multimedia subsystems mapped on multi-processor architectures. IEEE Trans. on Circuits and Systems for Video Technology, 1998. accepted for publication, Oct. 1998.
    • (1998) IEEE Trans. on Circuits and Systems for Video Technology
    • De Greef, E.1
  • 11
    • 0027590888 scopus 로고
    • An iteration partition approach for cache or local memory thrashing on parallel processing
    • May
    • J.Z. Fang et al. An iteration partition approach for cache or local memory thrashing on parallel processing. IEEE Trans. on Computers, C-42(5):529-546, May 1993.
    • (1993) IEEE Trans. on Computers , vol.C-42 , Issue.5 , pp. 529-546
    • Fang, J.Z.1
  • 13
    • 85050079654 scopus 로고
    • Implementing flexible computation rules with subexpression-level loop transformations
    • Aug
    • D. Kulkarni et al. Implementing flexible computation rules with subexpression-level loop transformations. In Proc. of the Euro-Par 95, Aug. 1995.
    • (1995) Proc. of the Euro-Par , vol.95
    • Kulkarni, D.1
  • 14
    • 0342699174 scopus 로고
    • A compiler-directed cache coherence scheme with improved intertask locality
    • Washington DC, Nov
    • L. Choi et al. A compiler-directed cache coherence scheme with improved intertask locality. In Proc. Supercomputing, Washington DC, Nov. 1994.
    • (1994) Proc. Supercomputing
    • Choi, L.1
  • 16
    • 0028745351 scopus 로고
    • Issues in multi-level cache design
    • Cambridge MA, Oct
    • L. Liu. Issues in multi-level cache design. In Proc. IEEE Int. Conf. on Computer Design, pages 46-52, Cambridge MA, Oct. 1994.
    • (1994) Proc IEEE Int. Conf. on Computer Design , pp. 46-52
    • Liu, L.1
  • 17
    • 85050130157 scopus 로고
    • Computer Systems Research Institute, Toronto, Canada, Mar
    • N. Manjikian et al. Technical Report CSRI-318, Computer Systems Research Institute, Toronto, Canada, Mar. 1995.
    • (1995) Technical Report CSRI-318
    • Manjikian, N.1
  • 19
    • 84955622341 scopus 로고    scopus 로고
    • A unified transformation technique for multi-level blocking
    • Lyon, France, Aug
    • M. Jimenez et al. A unified transformation technique for multi-level blocking. In Proc. EuroPar Conference, pages 402-405, Lyon, France, Aug. 1996.
    • (1996) Proc. EuroPar Conference , pp. 402-405
    • Jimenez, M.1
  • 20
    • 85050163949 scopus 로고
    • A study on the number of memory ports in multiple issue machines
    • Nov
    • S.-M. Moon et al. A study on the number of memory ports in multiple issue machines. In MICRO'26, pages 49-58, Nov. 1993.
    • (1993) MICRO'26 , pp. 49-58
    • Moon, S.-M.1
  • 21
    • 0031674554 scopus 로고    scopus 로고
    • Low power data transfer and storage exploration for h.263 video decoder system
    • Jan
    • L. Nachtergaele et al. Low power data transfer and storage exploration for h.263 video decoder system. IEEE Journal on Selected Areas in Communications, 16( 1):120-129, Jan. 1998.
    • (1998) IEEE Journal on Selected Areas in Communications , vol.16 , Issue.1 , pp. 120-129
    • Nachtergaele, L.1
  • 22
    • 0031997237 scopus 로고    scopus 로고
    • System-level power optimization of video codecs on embedded cores: A systematic approach
    • Feb
    • L. Nachtergaele et al. System-level power optimization of video codecs on embedded cores: A systematic approach. Kluwer Journal on VLSI Signal Processing, 18(2):89-109, Feb. 1998.
    • (1998) Kluwer Journal on VLSI Signal Processing , vol.18 , Issue.2 , pp. 89-109
    • Nachtergaele, L.1
  • 23
    • 0025470571 scopus 로고
    • Evaluation of the optimal strategy for managing the register file
    • O. Arregi et al. Evaluation of the optimal strategy for managing the register file. Microprocessing and microprogramming, (30):143-150, 1990.
    • (1990) Microprocessing and Microprogramming , vol.30 , pp. 143-150
    • Arregi, O.1
  • 24
    • 0022874874 scopus 로고
    • Advanced compiler optimizations for supercomputers
    • D.A. Padua et al. Advanced compiler optimizations for supercomputers. Communications of the AGM, 29(12):1184-1201, 1986.
    • (1986) Communications of the AGM , vol.29 , Issue.12 , pp. 1184-1201
    • Padua, D.A.1
  • 26
    • 0030193484 scopus 로고    scopus 로고
    • Image processing on high-performance risc systems
    • July
    • P. Baglietto et al. Image processing on high-performance risc systems. Proceeding of the IEEE, 84(7):917-930, July 1996.
    • (1996) Proceeding of the IEEE , vol.84 , Issue.7 , pp. 917-930
    • Baglietto, P.1
  • 27
    • 0025440459 scopus 로고
    • A survey of cache coherence schemes for multiprocessors
    • 12-24, June
    • P. Stenstrom. A survey of cache coherence schemes for multiprocessors. IEEE Computer, 23(6):12-24, June 1990.
    • (1990) IEEE Computer , vol.23 , pp. 6
    • Stenstrom, P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.