-
2
-
-
0028754935
-
Global communication and memory optimizing transformations for low power signal processing systems
-
J. Rabaey, P. M. Chau, and J. Eldon, Eldon, (IEEE Workshop on VLSI Signal Processing), IEEE Press, New York, Oct.
-
F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power signal processing systems," in VLSI Signal Processing VII, J. Rabaey, P. M. Chau, and J. Eldon, Eldon, (IEEE Workshop on VLSI Signal Processing), IEEE Press, New York, Oct. 1994, pp. 178-187.
-
(1994)
VLSI Signal Processing VII
, pp. 178-187
-
-
Catthoor, F.1
Franssen, F.2
Wuytack, S.3
Nachtergaele, L.4
De Man, H.5
-
3
-
-
0030383420
-
Power exploration for data dominated video applications
-
Monterey, CA, Aug.
-
S. Wuytack, F. Catthoor, L. Nachtergaele, and H. De Man, "Power exploration for data dominated video applications," in Proc. Int. Symp. Low Power Electron, and Design, Monterey, CA, Aug. 1996, pp. 359-364.
-
(1996)
Proc. Int. Symp. Low Power Electron, and Design
, pp. 359-364
-
-
Wuytack, S.1
Catthoor, F.2
Nachtergaele, L.3
De Man, H.4
-
4
-
-
0029181969
-
Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems
-
San Jose, CA, Aug.
-
L. Nachtergaele, F. Catthoor, F. Balasa, F. Franssen, E. De Greef, H. Samsom, and H, De Man, "Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems," in Rec. 1995 IEEE Int. Workshop Memory Technol., Design and Testing, San Jose, CA, Aug. 1995, pp. 82-87.
-
(1995)
Rec. 1995 IEEE Int. Workshop Memory Technol., Design and Testing
, pp. 82-87
-
-
Nachtergaele, L.1
Catthoor, F.2
Balasa, F.3
Franssen, F.4
De Greef, E.5
Samsom, H.6
De Man, H.7
-
5
-
-
0029474262
-
Memory organization for video algorithms on programmable signal processors
-
IEEE, Oct.
-
E. De Greef, F. Catthoor, and H. De Man, "Memory organization for video algorithms on programmable signal processors," in Computer Design: VLSI in Computers & Processors, IEEE, Oct. 1995, pp. 552-557.
-
(1995)
Computer Design: VLSI in Computers & Processors
, pp. 552-557
-
-
De Greef, E.1
Catthoor, F.2
De Man, H.3
-
6
-
-
0030407483
-
Low power storage exploration for H.263 video decoder
-
Nov.
-
L. Nachtergaele, F. Catthoor, B. Kapoor, S. Janssens, and D. Moolenaar, "Low power storage exploration for H.263 video decoder," in VLSI Signal Processing, Nov. 1996.
-
(1996)
VLSI Signal Processing
-
-
Nachtergaele, L.1
Catthoor, F.2
Kapoor, B.3
Janssens, S.4
Moolenaar, D.5
-
7
-
-
0025636693
-
DSP specification using the Silage language
-
Alburquerque, NM, Apr.
-
P. N. Hilfinger, J. Rabaey, D. Genin, C. Scheers, and H. De Man, "DSP specification using the Silage language," in Proc. Int. Conf. Acoust., Speech, and Signal Processing, Alburquerque, NM, Apr. 1990, pp. 1057-1060.
-
(1990)
Proc. Int. Conf. Acoust., Speech, and Signal Processing
, pp. 1057-1060
-
-
Hilfinger, P.N.1
Rabaey, J.2
Genin, D.3
Scheers, C.4
De Man, H.5
-
8
-
-
0030350235
-
System-level data-flow transformations for power reduction in image and video processing
-
Rhodes, Greece, IEEE, Oct.
-
F. Catthoor, M. Janssen, L. Nachtergaele, and H. De Man, "System-level data-flow transformations for power reduction in image and video processing," in Proc. Int. Conf. Electron., Circuits, and Syst., Rhodes, Greece, IEEE, Oct. 1996, pp. 1025-1028.
-
(1996)
Proc. Int. Conf. Electron., Circuits, and Syst.
, pp. 1025-1028
-
-
Catthoor, F.1
Janssen, M.2
Nachtergaele, L.3
De Man, H.4
-
10
-
-
0029288557
-
Trends in low-power ram circuit technologies
-
Apr.
-
K. Itoh, K. Sasaki, and Y. Nakagome, "Trends in low-power ram circuit technologies," in Proc. IEEE, vol. 83, pp. 524-543, Apr. 1995.
-
(1995)
Proc. IEEE
, vol.83
, pp. 524-543
-
-
Itoh, K.1
Sasaki, K.2
Nakagome, Y.3
-
11
-
-
84889230950
-
-
Feb.
-
Digital Video Coding at Telenor R & D, "Telenor's H.263 software, version 1.3," Feb. 1995, http://www.nta.no/brukere/DVC/ h263_software/.
-
(1995)
Telenor's H.263 Software, Version 1.3
-
-
-
12
-
-
0029356635
-
MPEG-2 video decoder for the digital HDTV grand alliance system
-
Aug.
-
A. Cugnini and R. Shen, "MPEG-2 video decoder for the digital HDTV grand alliance system," IEEE Trans. Consumer Electron., vol. 41, pp. 748-753, Aug. 1995.
-
(1995)
IEEE Trans. Consumer Electron.
, vol.41
, pp. 748-753
-
-
Cugnini, A.1
Shen, R.2
-
13
-
-
0028126173
-
A single-chip MPEG2 video decoder LSI
-
IEEE, Feb.
-
T. Demura et al, "A single-chip MPEG2 video decoder LSI," in Int. Solid-State Circuits Conf., IEEE, Feb. 1994. pp. 72-73.
-
(1994)
Int. Solid-State Circuits Conf.
, pp. 72-73
-
-
Demura, T.1
-
14
-
-
0029256367
-
An MPEG-1 audio/video decoder with run-length compressed antialiased video overlays
-
IEEE, Feb.
-
D. Galbi et al., "An MPEG-1 audio/video decoder with run-length compressed antialiased video overlays," in Int. Solid-State Circuits Conf., IEEE, Feb. 1995, pp. 289-287.
-
(1995)
Int. Solid-State Circuits Conf.
, pp. 289-1287
-
-
Galbi, D.1
-
16
-
-
0029254527
-
A single chip videophone encoder/decoder
-
IEEE, Feb.
-
M. Harrand, M. Henry, P. Chaisemartin, P. Mougeat, Y. Durand, A. Tournier, R. Wilson, J.-C. Herluison, J.-C. Langchambon, J.-L. Bauer, M. Runtz, and J. Bulone, "A single chip videophone encoder/decoder," in Int. Solid-State Circuits Conf., IEEE, Feb. 1995, pp. 292-293.
-
(1995)
Int. Solid-State Circuits Conf.
, pp. 292-293
-
-
Harrand, M.1
Henry, M.2
Chaisemartin, P.3
Mougeat, P.4
Durand, Y.5
Tournier, A.6
Wilson, R.7
Herluison, J.-C.8
Langchambon, J.-C.9
Bauer, J.-L.10
Runtz, M.11
Bulone, J.12
-
17
-
-
0029388046
-
VISI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HTDV video decoding
-
Oct.
-
T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa, "VISI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HTDV video decoding," IEEE Trans. Circuits Syst. Video Technol, vol. 5, pp. 387-395, Oct. 1995.
-
(1995)
IEEE Trans. Circuits Syst. Video Technol
, vol.5
, pp. 387-395
-
-
Masaki, T.1
Morimoto, Y.2
Onoye, T.3
Shirakawa, I.4
-
18
-
-
0345684803
-
A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 codec
-
IEEE, Feb.
-
M. Toyokura et al., "A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 codec," in Int. Solid-State Circuits Conf, IEEE, Feb. 1994, pp. 74-75.
-
(1994)
Int. Solid-State Circuits Conf
, pp. 74-75
-
-
Toyokura, M.1
-
19
-
-
0029354507
-
Development of an MPEG2 decoder for magneto-optical disk video players
-
Aug.
-
S. Ueda, Y. Kiyose, Y. Kishida, S. Sotoda, M. Kawabata, T. Furukawa, and S. Kawabe, "Development of an MPEG2 decoder for magneto-optical disk video players," IEEE Trans. Consumer Electron., vol. 41, pp. 521-527, Aug. 1995.
-
(1995)
IEEE Trans. Consumer Electron.
, vol.41
, pp. 521-527
-
-
Ueda, S.1
Kiyose, Y.2
Kishida, Y.3
Sotoda, S.4
Kawabata, M.5
Furukawa, T.6
Kawabe, S.7
-
20
-
-
2442547831
-
-
Boston, MA: Kluwer Academic
-
J. Vanhoof, K. van Rompaey, I. Bolsens, G. Goossens, and H. De Man, High-Level Synthesis for Real-Time Digital Signal Processing. Boston, MA: Kluwer Academic, 1993.
-
(1993)
High-Level Synthesis for Real-Time Digital Signal Processing
-
-
Vanhoof, J.1
Van Rompaey, K.2
Bolsens, I.3
Goossens, G.4
De Man, H.5
-
21
-
-
0017538003
-
A fast computational algorithm for the discrete cosine transform
-
Sept.
-
W.-H. Chen, C. H. Smith, and S. C. Fralick, "A fast computational algorithm for the discrete cosine transform," IEEE Trans. Commun., pp. 1004-1009, Sept. 1977.
-
(1977)
IEEE Trans. Commun.
, pp. 1004-1009
-
-
Chen, W.-H.1
Smith, C.H.2
Fralick, S.C.3
-
22
-
-
0029482162
-
Synthesis of pipelined DSP accelerators with dynamic scheduling
-
Cannes, France, Sept. ACM/IEEE
-
P. Schaumont, B. Van Thournout, I. Bolsens, and H. De Man, "Synthesis of pipelined DSP accelerators with dynamic scheduling," in Proc. 8th Int. Symp. System-Level Synthesis, Cannes, France, Sept. 1995, ACM/IEEE, pp. 72-77.
-
(1995)
Proc. 8th Int. Symp. System-Level Synthesis
, pp. 72-77
-
-
Schaumont, P.1
Van Thournout, B.2
Bolsens, I.3
De Man, H.4
-
23
-
-
2342568866
-
-
M. S. thesis, Delft Univ., Delft, The Netherlands, May
-
D. Moolenaar, "System specification and storage exploration for two video compression standards," M. S. thesis, Delft Univ., Delft, The Netherlands, May 1996, ftp: //ftp.imec.be/pub/vsdm/reports/video-codec _opt im/MPEG2_code_optim.ps.gz.
-
(1996)
System Specification and Storage Exploration for Two Video Compression Standards
-
-
Moolenaar, D.1
-
24
-
-
0344869069
-
Optimizing data transfers and memory for low power
-
accepted for publication
-
F. Catthoor, L. Nachtergaele, and S. Wuytack. "Optimizing data transfers and memory for low power," ASIC & EDA Mag., accepted for publication, 1997, ftp://ftp.imec.be/pub/vsdm/reports/ system_lev_power_opt/fc-asic_eda96.ps.gz.
-
(1997)
ASIC & EDA Mag.
-
-
Catthoor, F.1
Nachtergaele, L.2
Wuytack, S.3
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