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Volumn , Issue , 2001, Pages 560-564

A Boolean satisfiability-based incremental rerouting approach with application to FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN SATISFIABILITY; COMPLEX DESIGNS; ENGINEERING CHANGE ORDERS; FAULT SET; FUNCTIONAL SPECIFICATION; PHYSICAL FAULTS; RECONFIGURABLE DESIGNS; REROUTING ALGORITHMS;

EID: 84893678051     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915079     Document Type: Conference Paper
Times cited : (11)

References (13)
  • 2
    • 0026866240 scopus 로고
    • A detailed router for field programmable gate arrays
    • May
    • S. Brown, J. Rose, and Z. Vranesic, "A Detailed Router for Field Programmable Gate Arrays", IEEE Trans, on CAD, pp. 620-628, vol. 11, no. 5, May 1992.
    • (1992) IEEE Trans, on CAD , vol.11 , Issue.5 , pp. 620-628
    • Brown, S.1    Rose, J.2    Vranesic, Z.3
  • 4
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Trans, on Computers, pp. 677-691, 1986.
    • (1986) IEEE Trans, on Computers , pp. 677-691
    • Bryant, R.1
  • 5
    • 0033343886 scopus 로고    scopus 로고
    • An implicit connection graph maze routing algorithm for ECO routing
    • Nov.
    • J. Cong, J. Fang and K.-Y. Khoo, "An Implicit Connection Graph Maze Routing Algorithm for ECO Routing", Proc. IEEE/ACM ICC AD, Nov. 1999.
    • (1999) Proc. IEEE/ACM ICC AD
    • Cong, J.1    Fang, J.2    Khoo, K.-Y.3
  • 6
    • 84893691027 scopus 로고    scopus 로고
    • Efficient incremental rerouting for fault reconfiguration in FPGAs
    • Nov.
    • S. Dutt, V. Shanmugavel and S. Trimberger, "Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs", Proc. A CM/IEEE ICCAD, Nov. 1999.
    • (1999) Proc. A CM/IEEE ICCAD
    • Dutt, S.1    Shanmugavel, V.2    Trimberger, S.3
  • 7
    • 0031649068 scopus 로고    scopus 로고
    • Methodologies for tolerating cell and interconnect faults in FPGAs
    • Jan.
    • F. Hanchek and S. Dutt, "Methodologies for Tolerating Cell and Interconnect Faults in FPGAs", IEEE Trans. on Computers, vol. 47, no. 1, Jan. 1998.
    • (1998) IEEE Trans. on Computers , vol.47 , Issue.1
    • Hanchek, F.1    Dutt, S.2
  • 9
    • 0030679965 scopus 로고    scopus 로고
    • On two-step routing for FPGAs
    • April
    • G. Lemieux, S. Brown, and Z. Vranesic, "On Two-Step Routing for FPGAs", ISPD, pp. 60-66, April 1997.
    • (1997) ISPD , pp. 60-66
    • Lemieux, G.1    Brown, S.2    Vranesic, Z.3
  • 11
    • 0032649230 scopus 로고    scopus 로고
    • Satisfiability-based layout revisited: Detailed routing of complex FPGAs via search-based boolean SAT
    • Feb.
    • G. Nam, K. Sakallah, and R. Rutenbar, "Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based Boolean SAT", IntV Symposium on FPGAs, Feb. 1999.
    • (1999) IntV Symposium on FPGAs
    • Nam, G.1    Sakallah, K.2    Rutenbar, R.3
  • 12
    • 0032680865 scopus 로고    scopus 로고
    • GRASP: A search algorithm for propositional satisfiability
    • May
    • J. Silva and K. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability", IEEE Trans. on Computers, vol. 48, no. 5, May 1999.
    • (1999) IEEE Trans. on Computers , vol.48 , Issue.5
    • Silva, J.1    Sakallah, K.2
  • 13
    • 84893697534 scopus 로고    scopus 로고
    • http://www.xilinx.com/partinfo/databook.htm.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.